MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis

Dick, Robert P.; Jha, Niraj K.

doi:10.1007/978-1-4020-6488-3_22

Cited by 5 publications

(7 citation statements)

References 27 publications

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“…Tasks starting with yen are Yen's examples on p. 83 in [17]. Task dick is from [9]. These tasks were originally defined in different task models and do not possess all characteristics of a recurring real-time task.…”

Section: Resultsmentioning

confidence: 99%

Static priority scheduling of event-triggered real-time embedded systems

Erbas

Pimentel

Cerav-Erbas

2006

Form Method Syst Des

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Real-time embedded systems are often specified as a collection of independent tasks, each generating a sequence of event-triggered code blocks. The goal of scheduling tasks in this domain is to find an execution order which satisfies all real-time constraints. Within the context of recurring real-time tasks, all previous work either allowed preemptions, or only considered dynamic scheduling, and generally had exponential complexity. However, for many embedded systems running on limited resources, preemptive scheduling may be very costly due to high context switching and memory overheads, and dynamic scheduling can be less desirable due to high CPU overhead. In this paper, we study static priority scheduling of recurring real-time tasks. We focus on and obtain schedule-theoretic results for the non-preemptive uniprocessor case. To achieve this, we derive a sufficient (albeit not necessary) condition for schedulability under static priority scheduling and show that this condition can be efficiently tested in practice. The latter technique is demonstrated with examples, where in each case, an optimal solution for a given problem specification is obtained within reasonable time, by first detecting good candidates using meta-heuristics, and then by testing them for schedulability.

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Section: Resultsmentioning

confidence: 99%

Static priority scheduling of event-triggered real-time embedded systems

Erbas

Pimentel

Cerav-Erbas

2006

Form Method Syst Des

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“…At the same time, VFS opportunities are limited by the available slack in the schedule, and thus different task schedules must also be explored in order to optimize energy consumption [Schmitz et al 2002]. The VFS policy must consider the time/power overhead of mode transitions [Zhang et al 2003], and the energy consumption of system Dick and Jha [1999].…”

Section: Related Workmentioning

confidence: 99%

“…To explore different points in the design space, several steps are performed: resource allocation to determine the architecture, task mapping to enable the timing and power estimation, and task/voltage scheduling to meet the real-time deadlines and save power. Figure 1 shows an example flow of such a DSE process [Dick and Jha 1999]. It uses two nested genetic algorithms (GAs) to generate various system configurations with different resource allocations and task mappings.…”

Section: Design Space Explorationmentioning

confidence: 99%

Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling

Gorjiara

Bagherzadeh

Chou

2007

ACM Trans. Des. Autom. Electron. Syst.

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This paper presents a new technique, called Adaptive Stochastic Gradient Voltage-and-TaskScheduling (ASG-VTS), for power optimization of multicore hard realtime systems. ASG-VTS combines stochastic and energy-gradient techniques to simultaneously solve the slack distribution and task reordering problem. It produces very efficient results with few mode transitions. Our experiments show that ASG-VTS reduces number of mode transitions by 4.8 times compared to traditional energy-gradient-based approaches. Also, our heuristic algorithm can quickly find a solution that is as good as the optimal for a real-life GSM encoder/decoder benchmark. The runtime of ASG-VTS is 150 times and 1034 times faster than energy-gradient based and optimal ILP algorithms, respectively. Since the runtime of ASG-VTS is very low, it is ideal for design space exploration in system-level design tools. We have also developed a web-based interface for ASG-VTS algorithm.

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“…Dick et al [9] discuss bus synthesis as a part of the core-based synthesis tool, MOCSYN. Floorplanning and placement are iteratively conducted inside a feedback loop to obtain pointto-point delay estimation.…”

Section: Figure 1 Impact Of Layout Design On Bus Speedmentioning

confidence: 99%

“…Therefore, our methodology is considerably faster. Also our algorithm does not require the number of buses as an input constraint [9], since it can be only determined after the optimized bus structure is available.…”

Section: Figure 1 Impact Of Layout Design On Bus Speedmentioning

confidence: 99%

Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Thepayasuwan

Damle

Doboli

Proceedings 21st International Conference on Computer Design

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System level design always has a disadvantage of not possessing detailed knowledge of the communication sub-system. This is a crucial issue for System-on-Chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. The paper presents BA synthesis results for a network processor, and a JPEG SoC.

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MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis

Abstract: In this paper, we present a system synthesis algorithm, called MOCSYN, which

Cited by 5 publications

References 27 publications

Static priority scheduling of event-triggered real-time embedded systems

Static priority scheduling of event-triggered real-time embedded systems

Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling

Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

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