Model-Based Virtual Prototype Acceleration

Abstract

Today, virtual prototypes are often employed for software development early in the design flow. There, high simulation speed may support fast development. So, the acceleration of virtual prototype simulation is important in the early phases of design. To accelerate virtual prototypes, complex prototype simulation can be prevented by exploiting model-specific knowledge. We replace complex event-driven interaction with execution of predefined traces. In particular, we show that, for many dataflow-dominated application models, such accelerating traces may be efficiently determined. Trace determination is based on a novel symbolic search technique. We show that virtual prototypes exploiting such traces may lead to a significant simulation time reduction. The benefits are quantified for the prototype of a SystemC/TLM network packet filter, where traces result in up to 30% simulation acceleration.

A Survey of Virtual Prototyping Techniques for System Development and Validation

“…In the past several years, virtual platforms and virtual prototypes have been increasingly applied in hardware and software development, integration and validation before silicon devices are ready [6][7][8]. Virtual prototyping techniques have been widely explored and used by both industry engineers and academic researchers.…”

2012 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 31

“…Hu, Y. H., see 1767-1771 Huang, C.-P., see Lin, C.-W., TCAD Dec. 2012 Gladigau, J., TCAD Oct. 20121572-1585 Tenhunen, H., see Daneshtalab, M., TCAD Jan. 2012 146-159 Theocharides, T., see Kakoulli, E., TCAD March 2012 418-431 Thorolfsson, T., see Melamed, S., TCAD May 2012 676-689 Tian, H., Tang, W.-C., Young, E. F. Y., and Sze, C. N., Postgrid Clock Routing for High Performance Microprocessor Designs; TCAD Feb. 2012 255-259 Tolbert, J. R., see Zhao, X., TCAD Aug. 20121222-1234 Tomas, J., see Levi, T., TCAD Nov. 20121629-1641 Touba, N. A., see Yang, J.-S., TCAD Sept. 20121417-1427 1711-1722 Wang, W., see 1159-1168 Wang, Y., Zhang, Z., Koh, C.-K., Shi, G., Pang, G. K. H., and Wong, N., Pas-sivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation; TCAD April 2012 532-545 Wang, Y., see Gao, M., TCAD March 2012 356-369 Wang, Y., Hu, X., Cheng, C.-K., Pang, G. K. H., and Wong, N., A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints; TCAD Jan. 2012 109-120 Wang, Y., Hu, X., Cheng, C.-K., Pang, G. K. H., and Wong, N., Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints" ; TCAD March 2012 452 Wang, Z., see Fang, H., TCAD Oct. 20121586-1599 Wang, Z., see Fang, H Chung, J., TCAD Aug. 20121275-1287 Xiong, J., see Chung, J., TCAD April 2012 497-508 Xu, C., see Dong, X., TCAD July 2012994-1007 Xu, C., Srivastava, N., Suaya, R., and Banerjee, K., Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates; 1698-1710 Xu, Q., see Liu, X., TCAD Nov. 20121743-1753 Xu, Q.,...…”