Model checking on timed-event structures

Dasgupta, Pallab; Deka, Jatindra Kumar; Chakrabarti, P. P.

doi:10.1109/43.845084

Cited by 3 publications

(5 citation statements)

References 22 publications

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“…This paper shows that reasoning about the extremal timing properties of events can be done for efficiently than that of general extremal timing queries over timed event structures. The proposed logic, Min-max ETCTL, combines the ideas presented earlier (Dasgupta et al 2000(Dasgupta et al , 2001) into a unified logic for reasoning about extremal timing properties of events.…”

Section: Resultsmentioning

confidence: 99%

Min-max event-triggered computation tree logic

Dasgupta

Chakrabarti

Deka

2002

Sadhana

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Very often timing verification involves the analysis of the timings of discrete events such as signal changes, sending and receiving of signals, and sensitization of edge-triggered circuit components. The main bottleneck in verifying timing properties of timed finite state machines (FSM) has been the inherent complexity of verifying timed properties (PSPACE-complete for timed extensions of computational tree logic (CTL)). Often however, we are interested in the best case or worst case timings between events. In this paper we introduce a temporal query language called Min-max Event-Triggered Computational Tree Logic for expressing such extremal queries on the timings of events and show that such queries can be evaluated in time polynomial in the size of the system times the length of the formula.

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Section: Resultsmentioning

confidence: 99%

Min-max event-triggered computation tree logic

Dasgupta

Chakrabarti

Deka

2002

Sadhana

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“…Since we constrain all bounded-until formulas to appear in conjunction with trigger formulas, we effectively verify all timings with respect to event states only. This guarantees (and is formally proved in [6]) that ETCTL formulas satisfy the following property. We illustrate this fact through an example.…”

Section: L?mentioning

confidence: 71%

“…In a previous work [6], we addressed this problem and showed that this problem does not arise when we reason about the timings of events or signal changes. In that work we proposed a logic called ETCTL which is a real-time temporal logic for reasoning about the timings of events.…”

Section: L?mentioning

confidence: 97%

“…If a state and its parent have the same labeling, we remove that state from the original timed model and update the delay accordingly. Since ETCTL formulas are interval independent (as shown in [6]), the abstraction will preserve ETCTL properties. Table 2 show results computed on a 550 MHz Pentium-111 with Linux.…”

Section: Proofmentioning

confidence: 98%

“…The formal semantics is presented in [6]. Intuitively, the formulas posedge(B) and negedge(B) represent the positive edge and the negative edge of the signal defined by the boolean formula B.…”

Section: L?mentioning

confidence: 99%

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Abstractions for model checking of event timings

Deka

Chaki²,

Dasgupta³

et al.

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

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Verification of timed temporal properties of a circuit is a computationally complex problem both in terms of space and time. In this paper we study different abstractions of timed systems and the temporal logics which are preserved under these abstractions. In particular we show that while known timed logics such as RTCTL and TCTL are preserved by bisimulation equivalence, the timings of events (signal changes) are preserved in a more compact abstraction. Experimental results show that this abstraction requires significantly less space and is competitive in terms of time required for verification.

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