Characterization of plasma-induced Si substrate damage is demonstrated using an electrical capacitance-voltage (C-V) technique customized for the nano-scale analysis. Low resistive Si wafers are exposed to an inductively coupled plasma (ICP) or a capacitively coupled plasma (CCP). We focus on the effects of plasma parameters and wet-etching processes on plasma-induced physical damage (PPD) analyses. The optical thicknesses of surface and interfacial layers (d SL and d IL ) were characterized using spectroscopic ellipsometry (SE) and compared with the electrical oxide thicknesses (EOT) obtained by the C-V technique. In the case of asdamaged samples, the optical thickness d SL by SE is found to be smaller than the EOT by the C-V technique, while the sum of d SL and d IL was approximately equal to the EOT. A diluted hydrofluoric acid (DHF) wet-etch step is employed to address depth profile of defect density in damaged samples. We identify the latent defect density, d SL , and d IL after the DHF wet-etch, which are indispensible for practical device performance designs. It is found that, although the average energy of incident ions (Ē ion ) is larger for the case of CCP, the latent defect density of CCP-damaged samples is smaller than that of ICP even after the wet-etching. This finding is in sharp contrast to previous pictures-the largerĒ ion leads to the thicker damaged layer and the larger latent defect density. We propose a model for these conflicting results, where the profiles of defect density and the sensitivities of each analysis technique are taken into account. The present work highlights the importance of the nano-scale damage characterization using the C-V technique, allowing to understand the influence of latent defects and to enable better design of future electronic devices. Plasma processing plays an important role in manufacturing present-day microelectronics. Over the last two decades, plasma process-induced damage (PID) has been one of the crucial problems in fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs) 1-3 in LSI (Large Scale Integration) circuits. PID consists of four major mechanisms.2 The first mechanism is damage induced by conduction current from plasma flowing into MOSFETs, resulting in degradation of the performance and increase in the parameter variability owing to plasma-induced electrical stress. 1,4,5 This electrical interaction has been discussed and is called plasma-induced charging damage.2 The second mechanism is damage induced by incident photons on material surface. Photons with high energy can interact with materials such as photoresist masks and low-k dielectrics, leading to bond breaking in the materials exposed to plasma, or in some cases, create an interface state between SiO 2 and Si substrate.6-8 The third mechanism is surface and bulk chemical reaction with fast diffusion reactions causing material modification such as surface defects and roughness. The fourth mechanism is damage induced by high-energy ion bombardment on Si substrates or oth...