2004
DOI: 10.1007/978-3-540-30233-9_16
|View full text |Cite
|
Sign up to set email alerts
|

Modeling and Analysis of Dual Block Multithreading

Abstract: Instruction level multithreading is a technique for tolerating longlatency operations (e.g., cache misses) by switching the processor to another thread instead of waiting for the completion of a lengthy operation. In block multithreading, context switching occurs for each initiated long-latency operation. However, processor cycles during pipeline stalls as well as during context switching are not used in typical block multithreading, reducing the performance of a processor. Dual block multithreading introduces… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

1
1
0

Year Published

2012
2012
2018
2018

Publication Types

Select...
1
1

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
(2 citation statements)
references
References 15 publications
1
1
0
Order By: Relevance
“…A similar performance analysis of simultaneous multithreading, but using a slightly different model, was presented in [20]. All results presented there are very similar to results presented in this work which is an indication that the performance of simultaneous multithreaded systems is insensitive to (at least some) variations of implementation.…”
Section: Discussionsupporting
confidence: 79%
“…A similar performance analysis of simultaneous multithreading, but using a slightly different model, was presented in [20]. All results presented there are very similar to results presented in this work which is an indication that the performance of simultaneous multithreaded systems is insensitive to (at least some) variations of implementation.…”
Section: Discussionsupporting
confidence: 79%
“…A timed Petri net model of a pipelined processor [16] at the level of instruction execution is shown in Figure 1 (as usually, timed transitions are represented by solid bars, and immediate transitions by thin bars). For simplicity, only two levels of cache memory are represented in the model; it appears that such a simplification does not affect the results in a significant way [17]. It is assumed that the first-level cache does not delay the processor, while level-1 cache misses introduce the delay of t c processor cycles for level-2 cache hits and t m processor cycles for level-2 cache misses.…”
Section: Pipelined Processorsmentioning
confidence: 99%