Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Ojani, Amin; Mesgarzadeh, Behzad; Alvandpour, Atila

doi:10.1109/tcsi.2014.2321188

Cited by 7 publications

(32 citation statements)

References 17 publications

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“…Chapter 5 is based on Paper 1 [1] and analyzes the harmonic spur characteristic of edge-combining DLL-based frequency synthesizer. A comprehensive behavioral model of the spur magnitudes is introduced which includes the effects of the delay mismatch among the delay stages in the delay line, the static phase error (SPE) of the locked-loop due to the mismatches between up and down signals in the phase detector (PD) and charge pump (CP), and the duty cycle distortion (DCD) of the reference clock.…”

Section: Introductionmentioning

confidence: 99%

“…Chapter 6 covers Paper 1 and Paper 2 [1], [2] and presents the development of a prediction model for estimation of spurious performance in edge-combining DLL-based synthesizers. In order to develop the model, the introduced analytical model in Chapter 5 is further expanded using Taylor series approximations and moment methods, and closed-form expressions are obtained for the probability density function (PDF) and mean value of the harmonic spur magnitudes.…”

Section: Introductionmentioning

confidence: 99%

“…Chapter 7 is based on Paper 1 and Paper 2 [1], [2] and discusses the development of a spur-aware MC-free design flow for DLL-based synthesizers. It replaces the standard flow which is based on an iterative circuit-level modification-and-simulation approach.…”

Section: Introductionmentioning

confidence: 99%

“…In recirculating DLL-based approach [54]- [61], where the multiplied clock is generated by a similar mechanism as in a ring VCO-based PLL, the harmonic SCR is directly defined by the output frequency and the SPE of the locked-loop [60], [61]. In edge-combining DLL-based synthesizers [1]- [7] , [35], [36], [62]- [67], on the other hand, the carrier is generated by combining the equally-spaced DLL edges, and hence, misalignments of those edges result in periodic jitter and raise the reference harmonic spurs at the output spectrum of the synthesizer. These harmonic spurs can potentially downconvert the out-of-band interferers into the desired band.…”

Section: Introductionmentioning

confidence: 99%

“…In this chapter which is mainly based on [1], a comprehensive behavioral model of the edge-combining DLL-based synthesizers is developed which includes the impact of all the aforementioned sources of harmonic spurs in such synthesizers, i.e., DCD, SPE and delay mismatch. Fourier series representation of multiphase DLL outputs, an analytical model is developed which formulates the synthesizer SCR.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Analysis and design of a low jitter delay‐locked loop using lock state detector

Modanlou

Ardeshir

Gholami

2021

Circuit Theory & Apps

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Summary In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V.

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Open-loop all-digital delay line with on-chip calibration via self-equalizing delays

Antonov

Stadius

Kosunen

et al. 2017

2017 European Conference on Circuit Theory and Design (ECCTD)

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A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the external period and reference delay is then readjusted. When on-board settling monitor observes repetition of reference delay settings, it locks delay line by applying previously collected settings. The delay line is shown to lock in presence of 30% static offset of delays from their designed values. Furthermore, random spread of delays worsened by 3 times (5%PP to 15%PP) results in only 2% decline (3%PP to 5%PP) after applying the proposed calibration to 16-delays line.

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Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Cited by 7 publications

References 17 publications

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Analysis and design of a low jitter delay‐locked loop using lock state detector

Open-loop all-digital delay line with on-chip calibration via self-equalizing delays

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