Modeling and analysis of substrate coupling in integrated circuits

Gharpurey, Ranjit; Meyer, Robert G.

doi:10.1109/cicc.1995.518150

Cited by 76 publications

(74 citation statements)

References 2 publications

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“…Above the relaxation frequency of interfacial polarization, the inertia of majority carriers is not negligible and is defined by s = e Si AE q Si . Contrary to purely resistive previous crosstalk models [10,11], the relaxation time of majority carriers in the silicon substrate is not neglected and is modeled by the simple RC networks as presented in [12].…”

Section: Mos Capacitormentioning

confidence: 99%

Wideband characterization of SOI materials and devices

Raskin

2007

Solid-State Electronics

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Section: Mos Capacitormentioning

confidence: 99%

Wideband characterization of SOI materials and devices

Raskin

2007

Solid-State Electronics

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“…14. Then, the substrate calculation is performed with a boundary element method based on the Green functions [17], Fig. 15.…”

Section: Application Developed For Substrate Extractionmentioning

confidence: 99%

Mixed-signal IC design guide to enhance substrate noise immunity in bulk silicon technology

Valorge

Calmon

Andrei

et al. 2009

Analog Integr Circ Sig Process

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Predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve substrate parasitic voltage and substrate propagation are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. A typical study shows the possibility of such a method and measurements finally demonstrate its efficiency.

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“…Introduction: The interest in the monolithic integration of complex systems stems from its numerous advantages such as higher frequency performance, lower power consumption, reduced cost, reduced package pins, reduced package parasitics and increased reliability [1]. However, the continuous trend of electronics towards complete system-on-chip (SoC) solutions has made substrate noise coupling a serious concern for mixed-signal and RF design engineers trying to integrate a combination of sensitive low-noise circuits and noise-generating circuits in the same substrate.…”

mentioning

confidence: 99%

Impact of temperature on substrate coupling in low-doped substrate

2011

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The effect of temperature on substrate coupling is reported for the first time. Modelling and experimental results are presented, showing a significant linear dependence of the substrate resistance with temperature in the range between 257 and 418 K. The observed decrease in substrate resistance at lower temperatures implies that the substrate noise coupling could be seriously underestimated if the temperature effect is not taken into account. These results reveal the importance of including the effects of temperature on the substrate resistance models for the correct modelling of the substrate noise coupling.Introduction: The interest in the monolithic integration of complex systems stems from its numerous advantages such as higher frequency performance, lower power consumption, reduced cost, reduced package pins, reduced package parasitics and increased reliability [1]. However, the continuous trend of electronics towards complete system-on-chip (SoC) solutions has made substrate noise coupling a serious concern for mixed-signal and RF design engineers trying to integrate a combination of sensitive low-noise circuits and noise-generating circuits in the same substrate. The close proximity of these circuits leads to undesirable interactions between them through the common silicon substrate, which might affect their nominal functioning [2 -4].Operating temperature is an additional factor that is known to influence the performance and reliability of electronic circuits and, as such, it is always carefully considered in the device electrical models during the circuit design stage. High temperatures are known to decrease the mobility of carriers, enhance the injection of hot-carriers and increase the leakage current of junctions, thus reducing the performance of individual devices as well as of the circuits they are part of [5]. High temperatures are also known to raise latch-up susceptibility [6], accelerate the oxide breakdown of the transistors and aggravate electromigration in metal connections, thus having a negative impact on the reliability and lifetime of devices [5,7].Since temperature affects the mobility of carriers and junction capacitances, just to name a few, one should also expect temperature to influence the noise injected into the substrate, the noise susceptibility of circuits and/or devices and the noise propagation itself.Substrate noise coupling has long been linked to the finite resistance of the common substrate and as such good models of the substrate resistance are key to accurately model the substrate noise coupling early during the circuit's design stage [8,9]. However, to the best of our knowledge, the impact of temperature on substrate coupling has been completely ignored until now.This Letter investigates the impact of temperature in the substrate coupling for a low-doped substrate, showing that the temperature should indeed be accounted for in the substrate resistance models or else the substrate noise coupling may be seriously underestimated for the lower temperatures, consequently im...

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Modeling and analysis of substrate coupling in integrated circuits

Cited by 76 publications

References 2 publications

Wideband characterization of SOI materials and devices

Wideband characterization of SOI materials and devices

Mixed-signal IC design guide to enhance substrate noise immunity in bulk silicon technology

Impact of temperature on substrate coupling in low-doped substrate

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