Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability

Cho, Chang Burm; Zhang, Wangyuan; Li, Tao

doi:10.1109/mascot.2008.4770557

Cited by 5 publications

(2 citation statements)

References 36 publications

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“…Compared to a number of prior design space studies [21], [22], [8], [9], our PRIM-based approach is more efficient. First, traditional design space studies usually need to train a separate model for each benchmark.…”

Section: Efficient Generation Using Primmentioning

confidence: 99%

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Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules

Duan¹,

Zhang

et al. 2014

IEEE Trans. Comput.

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Soft errors have been significantly degrading the reliability of current processors whose feature sizes and supply voltages are fast scaling down. In this paper, we propose two effective approaches to characterize processor reliability against soft errors at presilicon stage. By utilizing a rule search strategy named Patient Rule Induction Method (PRIM), we are capable of generating a set of selective rules on key design parameters. These rules quantify the design space subregion with the lowest effective soft error rate (SER), thus providing useful guidelines in designing reliable processors. Furthermore, we also propose to use Classification and Regression Trees (CART) to partition the design space into a number of small subregions each being associated with a representative SER value. This gives the processor designer a global view of the SER distribution, enabling a comprehensive analysis over the entire design space. More importantly, both approaches generate "universal" models whose effectiveness is validated with a set of test programs unseen to training. Compared to traditional application-specific design space studies, our models' cross-program capability can save great training effort in the era of multithreading. Finally, a case study on multiprocessors is performed to simultaneously balance multiple design metrics, including reliability, performance, and power.

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Section: Efficient Generation Using Primmentioning

confidence: 99%

“…For the correlation between the AVF and configuration parameters, Cho et al [8], [9] predicted the dynamics of power, CPI, and the AVF using a combination of wavelets and neural networks. Our work differs from theirs in that we provide simple but useful guidelines to conduct reliable processor design.…”

Section: Related Workmentioning

confidence: 99%

Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules

Duan¹,

Zhang

et al. 2014

IEEE Trans. Comput.

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Protons Evaluation of 7nm Versal™ AI Engine (AIE) Based Radiation Tolerant Platform for Deep Learning Applications

Maillard,

Dhavlle,

Chen

et al. 2024

2024 IEEE Radiation Effects Data Workshop (REDW) (In Conjunction With 2024 NSREC)

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Mechanistic relationship between instruction fetch width and basic block size to architectural vulnerability factor

Huang

2016

2016 17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distribu

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Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability

Abstract: High performance and reliability are essential for microprocessor design. As

Cited by 5 publications

References 36 publications

Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules

Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules

Protons Evaluation of 7nm Versal™ AI Engine (AIE) Based Radiation Tolerant Platform for Deep Learning Applications

Mechanistic relationship between instruction fetch width and basic block size to architectural vulnerability factor

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