Modeling and characterization of CMOS-compatible high-voltage device structures

Design of a Class E Power Amplifier with LDMOS in Standard CMOS

“…Nevertheless, this requires a control of the doping, an option which is not available in qualified processes. One proposed solution readily available in CMOS with LOCOS, consists in using a low doping layer for the drift region in conjunction with a field plate to reduce the peak surface field at the drain-channel interface [10]. By doing this, a high breakdown voltage is possible.…”

“…As a consequence, during measurements it is possible to have device characteristics close to its optimum value. Within the devices devices tested -the conventional LDMOS [10] with and without field plate and new structures, the best results were obtained when using a low doping layer to decrease the electric field near the gate edge on the high doping drain side and at the same time to decrease the speed of the electrons reaching the drain lattice. The proposed solution (M 5 03 ) is depicted in Fig.…”

“…5. Unlike [10], it can be integrated in STI as well in LOCOS technologies. One advantage is that the drift region is not contaminated by the thick oxide growth.…”

“…Included are the results for the typical device (LV-MOS), the typical LDMOS device (M 2 02 [10]) and the proposed high-voltage transistor (LDMOS M 5 03 ). The two semicolon separated values represent the gate length and the oxide thickness over the thin and thick oxide.…”

A Simple Method to Analyze the Electrical Properties of High Power Lateral Double-Diffused Metal-Oxide-Semiconductor Transistors

“…are the gate and drain terminal voltage, respectively, and is the intermediate node voltage. 3) At low drain voltage , the drain current increases approximately linearly with the drain voltage because both transistors operate in the linear region. The drain current is given by 3) …”