Modeling and Characterization of Tungsten Chemical and Mechanical Polishing Processes

Abstract

Due to the complexity of chemical mechanical polishing ͑CMP͒ in general and metal CMP in particular, modeling of CMP processes has been pursued only minimally in the literature. A fundamental understanding of these metal CMP processes is needed to minimize manufacturing and development costs that will continue to escalate as more devices migrate to subhalf-micrometer technologies where metallization schemes are more complicated. In this work, we have used two different models to characterize the tungsten CMP process. While the chemical Preston model is used to explain the effect of process parameters on the mean polish rate, the slurry transport model is useful in explaining the within wafer uniformity for the polishing process. We successfully validated the chemical Preston model using design of experiment ͑DOE͒ data and demonstrated the importance of slurry transport and the pad to wafer gap, to the within wafer uniformity for the embossed and regular politex polishing pads. We showed that better uniformity is obtained throughout the wafer with the embossed politex than the regular politex pad due to the presence of grooves in the embossed pad, which allow for better slurry transport across the pad. We effectively characterized the process and studied the effects of changing the various tool and process parameters on process performance.As microprocessor, logic, and wireless device dimensions continue to scale down to the subhalf-micrometer size, chemical mechanical polishing ͑CMP͒ has become the enabling technology for the planarization of the dielectric, isolation, and metal layers in these devices. The advantages of using CMP for planarization are now well understood in the industry. 1 Metal CMP processes for via and contact planarization and dual Damascene processes are rapidly becoming some of the most critical processes in the manufacture of the next generation embedded and wireless devices. Tungsten ͑W͒ continues to be the metal of choice for filling contact and/or via holes for all complementary metal oxide semiconductor ͑CMOS͒ bipolar CMOS, memory, and high performance ͑HiP͒ technologies and devices. The removal of the W overburden by CMP to planarize the W in the contact and via holes is now a standard technique in the manufacturing of all these subhalf-micrometer multilevel devices.It has been shown in the literature that the metal CMP process is substantially more complicated than has been assumed. 2 In W CMP, there are many factors that affect the efficiency of the process. These factors vary from the effect of the W CMP tool itself such as the downforce and platen speed at which the CMP tool is run, to effects of the consumables such as pads and slurries that are used in processing of the wafers. Most of these factors interact with each other and it is a challenge to try to extract the individual contributions of each of these factors to process performance with factors such as the nonuniformity of the polish, and the removal rate of the W.In general, conventional experimental methods such as a de...

Optimization of tribological properties of silicon dioxide during the chemical mechanical planarization process

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Pads for IC CMP

“…It is shown that better uniformity is obtained throughout the wafer with the embossed politex pad than with regular politex pad because of the presence of grooves on the embossed pad [16]. For different patterns of grooves, combined patterns consisting of spiral and logarithmic grooves were shown to impact on several key attributes of the dielectric and copper CMP processes in terms of slurry retention, hydrodynamic pressure, tribological mechanism, and material removal rates [17].…”

Modeling the process of removal aimed at cut traces on semiconductor wafers by using the method of contactless chemical-and-dynamical polishing

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