Modeling and evaluation of substrate noise induced by interconnects

Martorell, F.; Mateo, D.; Aragones, X.

doi:10.1109/date.2003.1253662

Cited by 15 publications

(8 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…But the key limitation in mentioned macromodels is that they neglect the interconnect effect in their models. It has been shown in [10] that mediumsized interconnect can couple more noise into the substrate than several hundred switching transistors. So for having a high accuracy and an efficient macromodel, this noise source must be taken into account.…”

Section: Overview Of Substrate Noise Analysismentioning

confidence: 99%

An Efficient and Real time macromodel for Accurate and Fast Simulation of Substrate Coupling in Mixed-Signal IC's

Karimi

Mirzakuchaki

2006

2006 IEEE International Multitopic Conference

View full text Add to dashboard Cite

Substrate noise is a key problem in the design of large mixed-signal circuits. Estimating the interaction from large digital blocks and its effect on on-chip performance degradation is extremely important in mixed-signal IC design and is a major challenge in system-on-chip(SOC) design. In this paper, we address efficient methods and models to simulate substrate noise coupling at high level design with the real-time capability. An efficient, fast and real time macromodel is presented. Extracted macromodel captures a variety of noise interference mechanisms, including power/ground bounce, IR drop, switching coupling noise and interconnect noise sources. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are described. This approach makes it possible to predict substrate noise generation of large digital blocks in a very efficient and fast way and makes it compatible with the design flow of mixed-signal circuits. For verification, the macromodel accuracy is demonstrated in some example circuits.

show abstract

Section: Overview Of Substrate Noise Analysismentioning

confidence: 99%

An Efficient and Real time macromodel for Accurate and Fast Simulation of Substrate Coupling in Mixed-Signal IC's

Karimi

Mirzakuchaki

2006

2006 IEEE International Multitopic Conference

View full text Add to dashboard Cite

show abstract

“…The pure resistive model loses validity as frequency increases, committing reasonable error up to ∼4 GHz, but already significant above 7.5 GHz. Pads and wide interconnects have been divided in 20 µm pieces, and their parasitics coupled to the substrate model [18]. 50Ω resistors have been connected to the input and output pads to account for the network analyzer impedance.…”

Section: Measurements and Simulations On A Test Structurementioning

confidence: 99%

Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

2003

View full text Add to dashboard Cite

Crosstalk propagating through the silicon substrate is a serious limiting factor on the performance of advanced mixed analog-digital CMOS integrated circuits. This problem also appears in RF chips in the form of power leakage from local oscillators or power amplifiers, as well as noise coupled from the digital baseband circuitry. Several studies have presented measurements on simple test structures to determine the best approach to minimize this leakage. Nevertheless, these studies are usually restricted to a single technology, and the consequences of applying results to other technologies are not evaluated. Also, these studies are usually performed with on-wafer samples, and thus package effects are not taken into account. However, package parasitics are an important factor in substrate crosstalk, since they determine how much of the leakage finds a return path to external ground. In this paper, we discuss different technological approaches to increase isolation between coupled circuits. Measurements of the isolation on some test structures fabricated in a CMOS RF technology are presented. The package parasitics effect is evaluated by comparing on-wafer vs packaged samples. Measurement results are complemented with simulations of a broader range of situations.

show abstract

“…Moreover, oxide layers on top of the substrate may be defined as well. This offers the opportunity to simulate noise coupling between metal layers and the substrate which becomes more and more important as pointed out in [8]. Let Ω be the domain of the problem that comprises conductive layers with conductivity σ and insulating layers with permittivity ε as shown in Fig.…”

Section: Combined Substrate and Oxide Layer Modelmentioning

confidence: 99%

SubCALM: a program for hierarchical substrate coupling simulation on floorplan level

Brandtner¹,

Weigel²

Proceedings Design, Automation and Test in Europe Conference and Exhibition

View full text Add to dashboard Cite

The hierarchical substrate coupling simulation tool Sub-CALM offers the opportunity to estimate substrate coupling on floorplan level. A novel approach for modeling well and SOI structures in a boundary element description is introduced. Several acceleration techniques like precalculated macromodels and sophisticated preconditioning algorithms are presented which are applied to an O(n)-conjugate-gradient Poisson solver in order to be able to process large full-chip layouts during floorplanning.

show abstract

Modeling and evaluation of substrate noise induced by interconnects

Cited by 15 publications

References 7 publications

An Efficient and Real time macromodel for Accurate and Fast Simulation of Substrate Coupling in Mixed-Signal IC's

An Efficient and Real time macromodel for Accurate and Fast Simulation of Substrate Coupling in Mixed-Signal IC's

Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

SubCALM: a program for hierarchical substrate coupling simulation on floorplan level

Contact Info

Product

Resources

About