Modeling and Layout Optimization for Tapered TSVs

Lu, Tiantao; Srivastava, Ankur

doi:10.1109/tvlsi.2014.2384042

Cited by 12 publications

(2 citation statements)

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“…In addition, TSVs have to maintain a certain distance from each other, due to mechanical [Jung et al 2012;Lu et al 2016b] and signal integrity [Liu et al 2011] considerations. The TSV placement problem is to place the clock TSVs and control TSVs such that each TSV is located inside the layout area and outside other TSVs' keep-out-zones (KOZs) [Lu and Srivastava 2015b;Lu et al 2016c].…”

Section: Methodsmentioning

confidence: 99%

Low-Power Clock Tree Synthesis for 3D-ICs

Srivastava

2017

ACM Trans. Des. Autom. Electron. Syst.

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We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees' dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates' insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. Compared with previous 3D clock tree synthesis techniques, our Kmeans clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

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Section: Methodsmentioning

confidence: 99%

Low-Power Clock Tree Synthesis for 3D-ICs

Srivastava

2017

ACM Trans. Des. Autom. Electron. Syst.

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“…A vertical electrical connection called through-silicon-vias (TSVs) may act as media for transporting power supply or signals among layers of a 3D IC. Several techniques to construct these TSVs are discussed in literature [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Approach of genetic algorithm for power‐aware testing of 3D IC

Kaibartta

Giri

Rahaman

et al. 2019

IET Computers & Digital Techniques

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The interconnect between the cores of System-on-Chip (SOC) degrades the circuit performance by contributing to circuit delay and power consumption. To reduce this problem, SOC-based three-dimensional (3D) integrated circuit (IC) technology as a promising solution where multiple layers are stacked together decreasing the length of interconnect. However, 3D IC invites some new problems including more complexity in test generation. Testing of 3D IC requires test access architecture called Test Access Mechanism (TAM) for the purpose of transport of test stimuli to the cores placed in different layers. During testing due to increasing switching activity, any circuit demands higher power consumption and it becomes more acute for 3D IC. Moreover, testing of 3D ICs has other constraints. In this study, the authors address the issue of 3D IC testing using genetic algorithm-based approach to decrease test time. At first, available TAM width is partitioned into some fixed groups and they have to find partitioning of TAM and distribution of cores among layers with a goal to decrease test time. Next, they do the same considering, variable partitions with or without certain power limits. Experimental results establish the efficacy of the authors' method.

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