Modeling and Optimization of Edge Dislocation Stressors

IEEE Trans. Nanotechnology

2015

The dislocation stress memorization technique (D-SMT) stressor is demonstrated to boost the device performance on the Si three-dimensional (3-D) FinFET device. The larger channel stress and mobility enhancement ratio are observed in the narrower gate width device, due to the effect of triple crystal re-growth directions on the 3-D FinFET device. In this paper, ∼33% mobility enhancement and ∼23% Id,sat improvement on the Si FinFET device with W/L of 100/60 nm are achieved successfully with the implement of D-SMT stressor. Index Terms-Si, FinFET, stressor, dislocation-stress memorization technique (D-SMT).

Section: T He Dislocation-stress Memorization Technique (D-smt)mentioning

confidence: 99%

The Demonstration of Dislocation-Stress Memorization Technique Stressor on Si n-FinFETs

IEEE Trans. Nanotechnology

2015

The demonstration of a D-SMT stressor on Ge planer n-MOSFETs

2015

AIP Advances

An approximately 31% Id,sat improvement and 42% mobility enhancement are achieved on the planer Ge n-Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) by implementing the dislocation-stress memorization technology (D-SMT) stressor for the first time, based on an investigation of crystal re-growth velocities along different directions and the optimization of the dislocation angle (θ) in Ge. Ultra-high stress (>3 GPa) capping SiN film is found to be essential for modifying the crystal re-growth velocities along the [100] and [110] directions to optimize the θ. The change of crystal re-growth velocities and the mobility enhancement ratio with the stress along the assigned directions in Ge is also discussed, respectively.

The dependency of different stress-level SiN capping films and the optimization of D-SMT process for the device performance booster in Ge n-FinFETs

Applied Physics Letters

2015

The capping stressed SiN film is one of the most important process steps for the dislocation stress memorization technique (D-SMT), which has been used widely in the current industry, for the electron mobility booster in the n-type transistor beyond the 32/28 nm technology node. In this work, we found that the different stress-level SiN capping films influence the crystal re-growth velocities along different directions including [100] and [110] directions in Ge a lot. It can be further used to optimize the dislocation angle in the transistor during the D-SMT process and then results in the largest channel stress distribution to boost the device performance in the Ge n-FinFETs. Based on the theoretical calculation and experimental demonstration, it shows that the Ge three dimensional (3D) n-FinFETs device performance is improved ∼55% with the usage of +3 GPa tensile stressed SiN capping film. The channel stress and dislocation angle is ∼2.5 GPa and 30°, measured by the atomic force microscope-Raman technique and transmission electron microscopy, respectively.