Modeling and optimizing the costs of electronic systems

Scheffler, Michael; Ammann, D.; Thiel, A.; Habiger, C.; Tröster, Gerhard

doi:10.1109/54.706029

Cited by 13 publications

(7 citation statements)

References 8 publications

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“…where n is the number of rework attemps allowed, i.e., the maximum number of attempts to rework an individual part is n and N outi is number of parts passed by the test in the i th rework attempt (see (8) and associated discussion). When i=0, C 1 is the total cost of the parts that pass the test without ever going through diagnosis or rework.…”

Section: Diagnosis and Reworkmentioning

confidence: 99%

A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly

Trichy

Sandborn²,

Raghavan³

et al.

Proceedings International Test Conference 2001 (Cat. No.01CH37260)

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This paper presents a test/diagnosis/rework analysis model for use in technical cost modeling of electronic assemblies. The approach includes a model of test operations characterized by fault coverage, false positives, and defects introduced in test, in addition to rework and diagnosis operations that have variable success rates and their own defect introduction mechanisms. The model can accommodate an arbitrary number of rework attempts on any given assembly and can be used to optimize the fault coverage and rework investment during system tradeoff analyses. The model's implementation allows all inputs to the model to be represented as probability distributions thereby accommodating inevitable uncertainties in input data present during tradeoff activities and uses Monte Carlo methods to determine model outputs.

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Section: Diagnosis and Reworkmentioning

confidence: 99%

A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly

Trichy

Sandborn²,

Raghavan³

et al.

Proceedings International Test Conference 2001 (Cat. No.01CH37260)

View full text Add to dashboard Cite

show abstract

“…highdensity substrats with lines pitches less than 30µm, integrated de-coupling capacitors, high-density interconnect with about 4000 interconnects/cm 2 [6], threedimensional packaging technologies to shorten the signal lines and for high-speed communication also integrated optical interconnects. Co-design oriented CAD tools have to support the distributed functionality on the signal and clock level, in system partitioning [7], in thermics, and finally in the exploration of test, yield and costs [8].…”

Section: Barriers and Enabling Technologiesmentioning

confidence: 99%

Potentials of chip-package co-design for high-speed digital applications

Tröster

1999

Proceedings of the Conference on Design, Automation and Test in Europe

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The inherent potentials of the Si technology are limited by the low interaction with packaging. Co-design as the symbiosis between the ICs and appropriate high-density packaging offers lower RC line delay, improved SSN and lower costs compared to single-chip approaches. The distribution of the system functionality between IC and the packaging level opens up new vistas in future electronic design and system architecture. Roadmaps and co-design approachThe SIA roadmap for semiconductors [1] shows an undiminished performance increase of the inherent Si device technology over the next decade. But the overall system performance depends also on the packaging as the interconnect to the system environment. A low interaction between IC and packaging design will more and more limit the system potentials. The novel chip-package co-design approach with the objective of exploiting the synergism of ICs and packaging through their concurrent and matched design is clearly focused on system-level. For the challanges in high-speed digital design, clock delay, memory bandwidth, signal switching noise and cost/performance the co-design approach offers attractive solutions.

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“…In the electronics industry there are design analysis tools that include cost analysis. However, the cost estimation is an integral part of the tool's technical analysis and requires a large amount of detailed data before a cost estimation can be performed [5]. The detailed data is only available after the layout and routing design phase.…”

Section: Introductionmentioning

confidence: 99%

A Design-Centric Activity-Based Cost Estimation Model for PCB Fabrication

Giachetti

Arango

2003

Concurrent Engineering

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Electronic products are built in a competitive environment that demands constant miniaturization, increased functionality of each new generation of products, and compressed design cycles in order to be the first to market with a new product. One repercussion of these business conditions is the designer often does not have time to adequately explore all the design alternatives and select the best alternative. Tools are needed to aid the designer in evaluating the design early in the product development phase. Often reliable estimations of product cost are either lacking early in the design process or difficult and time-consuming to obtain. To address these problems an activity-based printed circuit board (PCB) cost estimation model is developed that estimates PCB cost based on the design parameters. The activities are defined so that the design decisions become the cost drivers and thus enable the cost estimation model to be utilized early in design process when sufficient time remains to make design changes. The cost model is used to rapidly compare different PCB design alternatives and lets the designer assess the impact of their decisions on final cost and aid the designer in generating lower cost alternatives. Analysis of the cost model reveals important relationships between design parameters and cost. The cost model is described and illustrated using a design example.

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Modeling and optimizing the costs of electronic systems

Cited by 13 publications

References 8 publications

A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly

A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly

Potentials of chip-package co-design for high-speed digital applications

A Design-Centric Activity-Based Cost Estimation Model for PCB Fabrication

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