Modeling and Simulation-Based Layout Optimization for Tolerance to TID Effect on n-MOSFET

Abstract

In the present study, the layout structure of an n-MOSFET, which is vulnerable to radiation, was designed in a different way to enhance its tolerance to radiation. Radiation damage assessment was conducted using modeling and simulation (M&S) techniques before actual semiconductor process fabrication and radiation tests to verify its tolerance properties. Based on the M&S techniques, the role of each layer was determined to improve the radiation tolerance of semiconductors, and the layout design of an n-MOSFET with enhanced radiation tolerance was optimized. The optimized radiation-tolerant n-MOSFET design was implemented in the 0.18-um CMOS bulk process, and radiation exposure tests were conducted on the device. A cumulative radiation dose up to 2 Mrad(Si) was applied to verify its radiation-tolerant performance. Developing new devices using M&S techniques for radiation damage assessment allows reliable estimates of their electrical and radiation-tolerant properties to be obtained in advance of the actual manufacturing process, thereby minimizing development costs and time.

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

“…Therefore, the fixed charge generated from the isolated oxide of the n-MOSFET should be reduced in an RH design of a CMOS logic circuit. This study proposes an RH CMOS logic circuit structure using an RH variable gate (V-gate) n-MOSFET [15] and standard p-MOSFET to prevent these fixed charges. In this section, we describe the RH V-gate n-MOSFET resistant to TID effects and the proposed RH CMOS logic circuit structure.…”

“…The ELT, DGA, L Style, and I-gate structures are representative examples of MOSFET structures with layout transformation techniques [8][9][10][11][12][13][14]. Among them, the RH variable-gate n-MOSFET, which is minimized in terms of its speed and area, provides various structural advantages to the design of RH circuits, considering that it can efficiently connect the electrodes of each device in the construction of a semiconductor integrated circuit (IC) [15]. Therefore, this study proposes an RH CMOS logic circuit that is constructed using n-MOSFETs with such structures, along with conventional p-MOSFETs.…”

“…Additionally, the channel size (W/L) of the device can be changed by adjusting the size of the RH layer. Therefore, radiation damage can be prevented regardless of the device size [11,15,19]. Unlike ELT and DGA n-MOSFETs, the W/L ratio of V-gate n-MOSFETs remains unchanged; therefore, the W/L size ratio must not be modified and process validation is possible during circuit design.…”

Simulation study on total ionizing dose effect of IGBT gamma irradiation

“…The TID effect refers to the long-term accumulated ionizing radiation effects. Currently, there is a large amount of research on the TID effect in semiconductor devices, but it mainly focuses on the TID effect in MOS devices [7]- [9] or the changes in transfer characteristics and output characteristics of IGBTs [1]. There is relatively less research on the comprehensive electrical characteristics of IGBTs in the space total dose radiation environment.…”