Modeling and Simulation of Highly Inductive On-Chip Interconnects

Abstract

Fig. la. The problem can be modeled by transmission lineIn the paper we present our approach to estimation of the (Fig. lb). The aim is to calculate the v2(t) voltage and to transmission lie sp restimate the influence of the line (R, L, C, d) and inverter (Rs, transissin lin ste resonse.The ain iea o the C0) parameters on the step response of the system. It iS known presented approach is to approximate the output signal of the lossy line, by analysis the behavior of the lossless transmission that the Laplace transform of the step response V2(t can be line. The output signal is expanded in the series of traveling expressedas: waves. We construct the conditions when the first incident V Es= E Zr(s) (l+po(s))e7(s)d wave of lossless line is good approximation of the step 2 s Rs + Zc (s) 1 -Po (s)p (s)e 27(s)d response of the line. where: Introduction + sL The faster circuits, shorter rise times, decrease of the Z, (s) =| C -characteristic impedance of the line, minimal feature size cause higher on-chip inductance effects [1,3]. The delay, overshoot, inductive crosstalk can no y(s) = ,(R + sL)sC -propagation coefficient, longer be ignored. Simulation of the VLSI circuit, including 1 interconnects, is a serious and difficult problem. Interconnects -Zc (s) simulation is often based on RLC transmission line model. Po (s) = sCO outputreflectioncoefficient There are many works on the output response and parameters 1 Z on e of the output signal approximations. Some of them try to find sCO + an easy formula to describe the interconnect behavior [2]. R -Z (s)

The low-loss interconnects simulation by perturbation methods

“…If we consider the long lines with 1 0 < Z R w [7] it is usually sufficient to consider only the first traveling wave without analyzing reflection.…”