Modeling capacitance of on-chip coplanar transmission lines over the silicon substrate

Compact Modeling and Comparative Analysis of Silicon-Chip Slow-Wave Transmission Lines With Slotted Bottom Metal Ground Planes

“…This follows since a resistive silicon substrate acts mainly as a capacitive loading effect to ground (namely, it has practically zero return current [7], [18]) so it only slows the wave in exactly the same manner as the slotted ground does. However, if the silicon-induced losses are significant, we simply get exactly these added silicon losses in the coplanar case (assuming still no return current in the silicon-which is shown to be a good assumption for a wide range of silicon resistivities and working frequencies [7], [18]), namely, that the losses in the above coplanar silicon structure will now be given by . This, of course, means that the slow-wave transmission line has lower losses per wavelength compared with the corresponding coplanar T-line above silicon.…”

“…We demonstrate the usefulness, validity, and excellent accuracy of this approach by full-wave EM simulations and -parameter measurements. A similar approach was previously used as a basis of compact transmission-line modeling method [7]- [9], and a brief summary of the model was presented in [10]. Manuscript and modeling approach.…”

On-chip CMOS coplanar transmission line measurements and model verification up to 50 GHz

“…The silicon substrate was removed from the quasi static Z element simulation setup since the collinear return current in the silicon was found to be negligible compared with the return current in the side shielding wires. However, the transverse currents in the silicon are significant and may lead to propagation losses as well as a frequency dependent Y element [2]. The results were verified by HFSS.…”

“…While microstrip T-lines [1] are used more in SiGe RF and millimeter wave designs, coplanar transmission lines [2] are used more in RF CMOS and high speed CMOS digital designs, where the high density Manhattan wire structure prevents from using the bottom metallic shield in most cases. Compact semi-analytical parametric models for these standard transmission line types have been developed as part of an interconnect-aware analog and mixed signal (AMS) design methodology [2,3] and integrated within the IBM CMOS design kits. In this paper we present and discuss the results of coplanar T-line measurements up to 50GHz and compare them with Ansoft EM solver results and the design kit coplanar models These structures are symmetrical and include grounded side shield lines.…”