Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Abstract

Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multicore revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies.This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (globally asynchronous locally synchronous) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion

“…Power gating the network devices according to the utilization was presented in [10], [11], and run-time NoC power management using DV(F)S was introduced in [12], [13]. Globally asynchronous locally synchronous (GALS) is another approach proposed as a low-cost and straightforward local power management strategy in complex SoCs owing to local synchronization and local clock generation [14]- [16].…”

Dense 3D Visual Mapping via Semantic Simplification

“…We have also shown how a state-of-the-art incremental mapping method can benefit from the proposed semantic point simplification to process less redundant data and to consequently speedup the mapping. As future work, we plan to evaluate viable energy efficient optimizations [33] for the proposed simplification procedure and we plan to design a flexible method able to deal with every semantic class, e.g., by identifying a per class simplification probability.…”

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

“…BlackOut has been fully implemented and integrated into an enhanced version [25,24] of the gem5 cycle-accurate simulator [2], extended in [25,24] to also include a cycle-accurate model of power gating in the NoC. DSENT [18] is used to extract power data of the simulated NoC architectures.…”