Modeling edge placement error performance of EUV and DSA multipatterning processes

Abstract

Background: Patterning of very tight pitches suffers from stochastic variations that can impact yield. Different patterning processes with lower stochastic variations are preferred when those lower variations have a quantifiable benefit in terms of device yield or performance. Aim: Here two different process flows, a traditional EUV patterning flow and one involving directed self-assembly (DSA) rectification, will be compared to determine the differences expected in device failure rates, with the failure mechanism being the shorting of a via hole to the wrong feature. Approach: These device failure rates will be based on a rigorous edge placement error (EPE) model taking stochastic variations into account, leading to predictions of device failure and the definition of an overlay process window (OPW): the range of overlay errors that keeps the device failure rate above a minimum specified value. Results: For the patterning of 18 nm pitch line/space patterns contacted with 12 nm wide vias, the EUV process flow produces a 2.5 nm OPW, while the DSA rectification process expands that OPW significantly to 4.0 nm. Conclusions: Using a rigorous EPE modeling approach fed by accurate stochastics measurements, the significant benefits of the DSA rectification process have been quantified.