Modeling Irradiation-Induced Degradation for 4H-SiC Power MOSFETs

Liang, Shiwei; Shu, Lei; Wu, Ziyuan; Chen, Bingru; Yu, Hengyu; Liu, Hangzhi; Wang, Liang; Li, Tongde; Deng, Gaoqiang; Wang, Daming

doi:10.1109/ted.2023.3234039

Cited by 15 publications

(2 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, the thermal cycling reliability of the designed packaging was improved. The following conclusions can be drawn from the study: (1) The most significant influence factor is solder thickness according to its degree of integrated influence for L, ε and R; (2) The optimal L, ε, and R performance of SiC MOSFET FOPLP were obtained when the x1, x2, x3, x4 were 0.4, 0.17, 0.1 and 0.2mm, respectively;…”

Section: Fatigue Lifetime Enhancementmentioning

confidence: 87%

“…Silicon carbide (SiC) exhibits excellent properties, such as high critical breakdown field strength, high thermal conductivity, and high electron saturation velocity compared to Si material [1,2]. Thus, SiC MOSFET has comparative advantages over Si-MOSFET in terms of switching speed, junction temperature operation, and energy loss enabling a significant improvement in energy density and reduced weight and the volumetric ratio [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm

Chen

Yan

Ibrahim³

et al. 2023

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

As the next generation of semiconductor devices, SiC MOSFETs have demonstrated significant performance improvements in switching loss, switching frequency, and hightemperature operation compared to Si-based MOSFETs. However, the long-term reliability of such devices and their packaging continues to be a major concern. Towards addressing this challenge, this study proposes a multi-objective optimization design method for parasitic inductance (L), thermal strain (ε), and thermal resistance (R) of SiC MOSFETs with Fan-Out Panel-Level Packaging (FOPLP). First, the orthogonal experimental design was employed to investigate the thickness effects of baseplate, solder, die and redistribution layer (RDL) on L, ε, and R. Then, the multiobjective optimization was developed to simultaneously reduce L, ε, and R. Finally, the fatigue lifetimes of the optimized and initial SiC MOSFET FOPLP structures were compared to verify the optimization's accuracy. Study findings include: (1) Solder thickness was the most significant influence factor for L, ε and R of SiC MOSFET FOPLP, L and R increased, and ε decreased with increasing solder thickness; (2) The proposed multi-objective optimization method coupled with a genetic algorithm achieved 14.79, 8.96, and 9.28% reduction of L, ε, and R, respectively; (3) The fatigue lifetime of solder (SAC305) was evaluated using the Coffin-Manson model, with predicted lifetimes before and after optimization being 6786 and 7085 cycles, respectively, demonstrating that the proposed approach significantly enhanced the designed SiC MOSFET FOPLP's long-term thermal cycling reliability.

show abstract

Section: Fatigue Lifetime Enhancementmentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm

Chen

Yan

Ibrahim³

et al. 2023

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

show abstract

Degeneration mechanism of 30 MeV and 100 MeV proton irradiation effects on 1.2 kV SiC MOSFETs

Seo,

Kim,

Kang

et al. 2025

Radiation Physics and Chemistry

View full text Add to dashboard Cite

Comparison of total ionizing dose effects in SiC MOSFETs with double trench versus asymmetric trench

Cao,

Chang,

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

The SiC metal-oxide-semiconductor field effect transistor (MOSFET), as a third-generation wide-bandgap semiconductor, possesses advantages such as low on-resistance, high power density, fast switching speed, and low switching losses, making it a promising candidate in aerospace equipment. However, electrons in space can cause total ionizing dose (TID) effects, leading to the performance degradation of electronic components, especially in deep space environments with high-energy and high-flux electron irradiation. In this study, electron irradiation induced TID effects were experimentally investigated in SiC MOSFETs with different structures of double trench (DT) and asymmetric trench (AT). The DT-MOSFET was found to be more sensitive to TID effects. Furthermore, the technology computer aided design (TCAD) simulation was performed to reveal the mechanism of the trench structure dependent TID effects. It was revealed that compared to DT-MOSFET, the semi-enclosed P+ well structure in the AT-MOSFET provides protection to the bottom of the gate oxide layer, reducing the electric field intensity in that region and suppressing the impact of TID effects.

show abstract

Modeling Irradiation-Induced Degradation for 4H-SiC Power MOSFETs

Cited by 15 publications

References 16 publications

Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm

Thermal-mechanical-electrical Co-design of Fan-Out Panel-Level SiC MOSFET Packaging with a Multi-objective Optimization Algorithm

Degeneration mechanism of 30 MeV and 100 MeV proton irradiation effects on 1.2 kV SiC MOSFETs

Comparison of total ionizing dose effects in SiC MOSFETs with double trench versus asymmetric trench

Contact Info

Product

Resources

About