Modeling networking issues of network-on-chip: a coloured petri nets approach

Abstract

Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-ona-chip (SoC). As current verification techniques for on-chip communication algorithms are typically complicated tasks including many hardware modules and software routines, verifying the algorithms themselves is almost impossible. Having the incentive for simplifying verification of these on-chip algorithms, in this paper, we propose a detailed NoC CPN model in which key NoC networking challenges, namely network topology, switching method, and routing algorithm are considered. By this model, any desired NoC topologies, including but not limited to, mesh and k-ary ncube can be constructed. As for switching techniques, dominant on-chip switching methods, namely, packet switching, circuit switching, and wormhole switching, are modeled. Besides, as model of a NoC switch element is highly dependent on its switch fabric type, different sorts of switching fabrics, i.e., crossbar and shared bus, are modeled in this contribution. For routing the packets between cores, a CPN version of dimension-ordered routing, dominant routing algorithm for NoC, is implemented in the switches.

Modeling and Verification of Network-on-Chip using Constrained-DEVS

“…Although the approach suggested in (Goossens, et al 2005) is simplistic due to the assumed determinism, it is important that we consider this approach and expand on it in order to bring forth more comprehensive performance verification methods. In another approach, Petri nets were used to verify routing and switching policies in NoC (Bazzaz, et al 2009).…”