Modeling of gate-induced drain leakage current in <i>n</i>-type metal–oxide–semiconductor field effect transistor

Touhami, Ahmed; Bouhdada, A.

doi:10.1063/1.1327607

Cited by 7 publications

(2 citation statements)

References 11 publications

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“…Another important point interesting to evaluate in a NOR-architecture memory array is the BitLine Leakage (BLL), due to the Gate Induced Drain Leakage (GIDL) current in Band-to-Band Tunneling (BBT) regime, during the CHE programming operation [15]. As highlighted in previous studies [16][17][18], several technological parameters, such as cell LDD doping (dose, tilt, and energy), drain-gate overlap, or STI shape have an impact on electric fields in the drain-bulk junction, responsible for GIDL. In this section, the impact of arsenic LDD implantation energy on bitline leakage measurements is presented through electrical characterizations, performed on a -dummy cell‖ structure.…”

Section: Bitline Leakage Optimizationmentioning

confidence: 97%

Push the flash floating gate memories toward the future low energy application

Marca¹,

Just²,

Régnier³

et al. 2013

Solid-State Electronics

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In this paper the consumption of Flash Floating Gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances and reliability. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

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Section: Bitline Leakage Optimizationmentioning

confidence: 97%

Push the flash floating gate memories toward the future low energy application

Marca¹,

Just²,

Régnier³

et al. 2013

Solid-State Electronics

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“…The presence of the gateinduced high electric field entails the overlap of the silicon energy bands and breeds the emission of minority carriers, which will be in transit, because of the BBT effect, from the valence band to the conduction band of silicon. The electrons emitted at the surface of the deep depletion region layer are collected by the drain and moved towards the substrate under the transverse electric field giving, therefore, a leakage current that is described by [16]:…”

Section: Gate-induced Drain Leakage Currentmentioning

confidence: 99%

The n-type metal oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

Touhami¹,

Bouhdada²

2002

Semicond. Sci. Technol.

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The band-to-band tunnelling (BBT) effect in an n-type metal-oxide semiconductor field-effect transistor (n-MOSFET) is attributed not only to the transverse electric field E T but also to the lateral electric field E L in the gate-to-drain overlap region. The main sources of these electric fields are the gate-source (V gs ) and drain-source (V ds ) voltages. The modelling of the gate-induced drain leakage current, I gidl , associated with BBT remains always dependent on the drain-gate voltage, V dg , whatever the applied values of V gs and V ds , which cannot describe accurately the evolution of the I gidl current according to biases. Therefore, it is necessary to clarify the impact of V gs and V ds separately. In this paper, we propose a new model of the I gidl current, which can describe the BBT effect in n-MOSFETs under various V gs and V ds biases.

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