Modeling of layout-dependent stress effect in CMOS design

Abstract

Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process

“…But it brings in complex modeling and increases the computational time for circuit simulation. A piecewise linear approximation having a bathtub is reported by Wang et al [6]. It allows the integration and outputs with an analytical formula, ready for the compact model.…”

“…For the mobility, two kinds of stress-induced mobility model are used for better accuracy or less modeling complexity. The stress dependent threshold voltage shift is considered by assuming that the flat-band voltage variation under the strain is linearly proportional to the applied stress [6].…”

“…The ΔE(x) can be obtained based on a function of deformation potential constants (P) [11,14] at a certain applied stress (σ) as ΔE(x)=P·σ(x) [6]. For the equivalent hole mobility, a simplified model of the band structure model i.e.…”

“…To handle LDE by unintentional and intentional stresses, several LDE models exist based on a physical approach, but these have been focused on one-dimensional effects or limited layout parameters tested down to 45 nm technology node [5][6][7][8].…”

“…(The gate positions of 1, 2, 4, 5 are for asymmetric case (SA≠SB) and 3 for the symmetrical one (SA=SB)) Fig. 2 Concept of bathtub approximation for parabolic stress profile[6].…”