Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs

Ahmad, Waqar; Chen, Qiang; Zheng, Lirong; Tenhunen, Hannu

doi:10.1007/s10470-011-9797-0

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2021

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“…Many efforts have been made to reduce the capacitance, including low-k dielectric bilayer liner 17) and thicker dielectric layer, 18) etc. Several elaborate capacitance models have been proposed 19,20) to analytically calculate the coupling capacitance with consideration of the Metal-oxide-semiconductor effects between TSVs and the substrate. However, these models can only handle a very small TSV cluster.…”

Section: Introductionmentioning

confidence: 99%

Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

Zhao

Sun

et al. 2021

Jpn. J. Appl. Phys.

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Signal integrity in high density through silicon via (TSV) has become a key concern in 3D integrated circuits design as its continuous scaling down. In this paper, the corner/edge effect of TSV arrays is proven to be non-neglectable and is characterized by coupling capacitance, mutual inductance, S parameter, and maximum noise respectively. The 6C static shielding method (X. Cui et al., ICEPT, 2018, p. 944) is improved by inserting ground TSVs at the array corners according to our evaluation. At last, we proposed three layout optimization rules for TSV interposer design to generate a more balanced electromagnetic shielding and to achieve better signal integrity.

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Section: Introductionmentioning

confidence: 99%