Modeling of Read Disturbance Mechanism due to Carrier Trapping in Sub-20nm NAND Flash Memory

Kang, Duck Hee; Lee, K.; Kwon, Sin; Kim, S.; Hwang, Yoohwa; Shin, Hyungcheol

doi:10.7567/ssdm.2014.a-2-5l

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2015

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“…In a previous research, 27) we modeled read disturbance mechanism observed at PV1 and ERS in sub-20 nm NAND flash memory. In this paper, we show the dependence of read disturbance mechanism on the temperature and analyze the characteristics of read disturbance mechanism more in detail.…”

Section: Introductionmentioning

confidence: 99%

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

Kang¹,

Lee²,

Kwon³

et al. 2015

Jpn. J. Appl. Phys.

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We observed an increase of V th by read disturbance mechanism at programmed threshold voltage state (PV1) and erase state (ERS) states in retention characteristics of sub-20 nm NAND flash main-chip. We also confirmed that the charge gain behavior by read disturbance has dependency on the number of read and cycling operations. As a result, we quantitatively modeled read disturbance mechanism by the amount of final ΔV th and deterioration coefficient α which is related to the number of read operation times. It was also observed that those parameters increase with increasing cycling times and have larger value at ERS state than that at PV1 state.

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Section: Introductionmentioning

confidence: 99%