Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

Zhang, Xianjun; Yang, Yong; Duan, Baoxing; Chai, Changchun; Song, Kaijun; Chen, Bin

doi:10.1088/1674-1056/21/3/037303

Chinese Phys. B

2012

DOI: 10.1088/1674-1056/21/3/037303

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Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

Xianjun Zhang¹,

Yong Yang²,

Baoxing Duan³

et al.

Abstract: Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor *Zhang Xian-Jun( ) † , Yang Yin-Tang( ), Duan Bao-Xing( ), Chai Chang-Chun( ), Song Kun( ), and Chen Bin( )

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Cited by 2 publications

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Reliability-Aware Support Vector Machine-Based High-Level Surrogate Model for Analog Circuits

Khandelwal

Garg

Boolchandani

2015

IEEE Trans. Device Mater. Relib.

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Negative Bias Temperature Instability (NBTI) has deleterious impact on threshold voltage and drive current of PMOS transistor. In this paper, a Support Vector Machine (SVM) based Surrogate Model for NBTI phenomenon is developed within the framework of the HSPICE MOSRA (MOSFET Reliability Analysis) model, for Gain and Slew-Rate of Differential Amplifier. Feasibility Space identification and Adaptive Learning scheme are applied to improve the results using less number of training samples which reduces run time. A single Performance Parameter evaluation of complete circuit requires 0.046 ms and 0.03 ms for Gain and Slew-Rate respectively, which shows significant improvement over previous methodology. This surrogate model is validated by finding Correlation Coefficient between SVM model and HSPICE. The values of Correlation Coefficients are 0.9979 and 0.9997 for Gain and Slew-Rate respectively.

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Reliability-Aware Support Vector Machine-Based High-Level Surrogate Model for Analog Circuits

Khandelwal

Garg

Boolchandani

2015

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

show abstract

New REBULF super junction LDMOS with the N type buffered layer

段宝兴¹,

曹震²,

袁小宁³

et al. 2014

Acta Phys. Sin.

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In this paper, a new REBULF (reduced BULk field) SJ-LDMOS (lateral double-diffused MOSFET) is proposed with the N type buffered layer based on the buffered SJ-LDMOS for the low loss of LDMOS used in the power integrated circuits. In this structure, the problem of the substrate-assisted depletion, produced due to the P-type substrate for the N-channel SJ-LDMOS, is eliminated by the N-type buffered layer. The charges for the N-type and P-type pillars are depleted completely. Moreover, a new electric field peak is introduced into the surface electric field distribution, which makes the lateral surface electric field uniform. The breakdown voltage is improved for the REBULF SJ-LDMOS in virtue of the ISE simulation results. By optimizing the location and parameters of the N-type buried layer, the breakdown voltage of REBULF SJ-LDMOS is increased by about 49% compared with that of the conventional LDMOS, and improved by about 30% compared with that of the buffered SJ-LDMOS.

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Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

Abstract: Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor *Zhang Xian-Jun( ) † , Yang Yin-Tang( ), Duan Bao-Xing( ), Chai Chang-Chun( ), Song Kun( ), and Chen Bin( )

Cited by 2 publications

References 15 publications

Reliability-Aware Support Vector Machine-Based High-Level Surrogate Model for Analog Circuits

Reliability-Aware Support Vector Machine-Based High-Level Surrogate Model for Analog Circuits

New REBULF super junction LDMOS with the N type buffered layer

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