Modeling of the Section Capacitance to Interface with a S3R

Abstract

Cell capacitance is a well-known parameter in silicon solar cells. Its effects on the power units, specially on the S3R, is also well known since it has to be taken into account to design them. The capacitor energy is discharged into the power switch and the dissipation increases. Moreover, it introduces a delay in the energy transfer from the array to the main power bus. In triple junction solar cells, this parasitic element becomes far more complex and is not so well characterized. This paper addresses this issue and proposes a large signal model to be used in combination with a S3R.

Sequential Switching Shunt Regulator Parallel Power Processing Control for High Capacitance Solar Arrays

“…The parasitic capacitance used for the simulations is based on the Azurspace 3G28 solar cell capacitance studies presented in [12]; a 2.25 µF capacitance per cell (0.5 A Isc, 2.5 V Voc) is proposed in this paper. For a 50 V bus, twenty cells in series are needed in each solar array section so the resultant parasitic capacitance is 225 nF/A.…”

“…The fine current balance is achieved with the first small power section. The total load-averaged current is given by Equation (12).…”

Comparative Study of SiC Transistors for Active Current Limitation in S3R

“…3 are neglected. The solar array parasitic capacitance stored energy can be expressed as (5), therefore, if the transistor must dissipate this energy, we have an expression like (6):…”

“…Two facts are the main causes for the increase of solar section parasitic capacitance, increase of individual cell capacitance due to multi-junction technologies and larger sections with many strings in parallel. Currently, parasitic capacitances values reach few microfarads [5].…”