Modeling Power Consumption of NAND Flash Memories Using FlashPower

Mohan, Vidyabhushan; Bunker, Trevor; Grupp, Laura M.; Gurumurthi, Sudhanva; Stan, Mircea R.; Swanson, Steven

doi:10.1109/tcad.2013.2249557

Cited by 39 publications

(17 citation statements)

References 21 publications

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“…The F-N tunneling occurs when the applied electric field between the substrate and the CG is sufficiently large to overcome the potential barrier if the FG is charged. F-N tunneling is widely employed in actual flash memories since the voltage required for the write operation is lower than in HEI-based memory cells [33,34,35]. …”

Section: Technical Backgroundmentioning

confidence: 99%

“…An SLC flash performs the read operation in only one stage, which involves lower read/write access time than any of the multi-level technologies [33]. In particular, in comparison with SLC technology, MLC requires up to four times more time to write and 2.5 times more to read [36].…”

Section: Technical Backgroundmentioning

confidence: 99%

“…To figure out the energy consumption associated with SLC and MLC NAND flash technologies, we refer to the comparison between both as reported in [33]. The energy per bit estimated in the write operation using SLC is 305 pJ, whereas for MLC it is 1200 pJ.…”

Section: Technical Backgroundmentioning

confidence: 99%

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Nanotechnology is an emerging scientific area whose advances, among many others, have a positive direct impact on the miniaturization of electronics. This unique technology enables the possibility to design and build electronic components as well as complete devices (called nanomachines or nanodevices) at the nano scale. A nanodevice is expected to be an essential element able to operate in a nanonetwork, where a huge number of them would coordinate to acquire data, process the information gathered, and wirelessly transmit those data to end-points providing innovative services in many key scenarios, such as the human body or the environment. This paper is aimed at studying the feasibility of this type of device by carefully examining their main component parts, namely the nanoprocessor, nanomemory, nanoantenna, and nanogenerator. To this end, a thorough state-of-the-art review is conveyed to discuss, substantiate, and select the most suitable current technology (commercial or pre-commercial) for each component. Then, we further contribute by developing a complete conceptual nanodevice layout taking into consideration its ultra-small size (similar to a blood cell) and its very restricted capabilities (e.g., processing, memory storage, telecommunication, and energy management). The required resources as well as the power consumption are realistically estimated.

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Section: Technical Backgroundmentioning

confidence: 99%

Section: Technical Backgroundmentioning

confidence: 99%

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Conceptual Design of a Nano-Networking Device

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show abstract

“…12 where P avg is the average power consumption of the specific SSD devices involved. A reference estimation for the above power consumption values (that however are very NAND flash device-dependent) comes from the models and hardware details presented in [33][39] and [7].…”

Section: Disk Solicitation Energy-oriented Attacksmentioning

confidence: 99%

Energy-oriented denial of service attacks: an emerging menace for large cloud infrastructures

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This work analyzes a new and very subtle kind of security threat that can affect large scale cloudbased IT service infrastructures, by exploiting the computational resources of their component data center in order to waste as much energy as possible. The consequence of these threats range from increased costs in the energy bill, to penalization for exceeding the agreed quantity of green house gases (GHG) emissions, up to complete denial of service caused by electrical outages due to power budget exhaustion.We analyzed the different types of such attacks with their potential impacts on the energy consumption, modeled their behavior and quantified how current energyproportional technologies may provide attackers with great opportunities for raising the target facility emissions and costs. These efforts resulted in a simple model with some parametric reference values that can be used to estimate the impact of such attacks also in presence of very large infrastructures containing thousands or

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“…A log-based write strategy has been proposed at the MTD layer to provide extra ECC redundancy. Other works focus on the crash recovery [20], [21], energy optimization [22], or real-time performance [23] of NAND flash memory storage systems. Although recent literatures have investigated from the perspective of the file system and hardware implementation of flash, they have not yet explored opportunities at the level between file system and flash translation layer, with the resulting advantage that no changes are required to the file system, cache hierarchy, or hardware implementation of the flash memory chip.…”

Section: Introductionmentioning

confidence: 99%

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems

Wang

Huang

Shao

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibit errors. NAND flash memory is normally used to store the file system metadata and page mapping information. Thus, a broken physical page containing metadata may cause an unintended and severe change in functionality of the entire flash. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multibit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-chip hierarchy, or hardware implementation of flash memory chip. We evaluate Meta-Cure under a real-embedded platform using a variety of I/O traces. The evaluation platform adopts dual ARM Cortex A9 processor cores with 64 Gb NAND flash memory. We have evaluated the effectiveness of Meta-Cure on the new technology file system file system. Experimental results show that the proposed technique can reduce uncorrectable page errors by 70.38% with less than 7.86% time overhead in comparison with conventional error correction techniques.

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Modeling Power Consumption of NAND Flash Memories Using FlashPower

Cited by 39 publications

References 21 publications

Conceptual Design of a Nano-Networking Device

Conceptual Design of a Nano-Networking Device

Energy-oriented denial of service attacks: an emerging menace for large cloud infrastructures

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems

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