Proceedings of the 24th Asia and South Pacific Design Automation Conference 2019
DOI: 10.1145/3287624.3287630
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Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline

Abstract: Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) are two major techniques for reducing energy consumption in such embedded systems. Furthermore, MPSoCs are becoming more popular for many real-time applications. One of the challenges of integrating DPM with DVFS and task scheduling of real-time applications on MPSoCs is the modeling of idle int… Show more

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Cited by 8 publications
(15 citation statements)
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“…Therefore, the ratio between e j,0 and e j,1 for each job j needs to reflect the ratio between the dynamic energy consumption of the processor on machine 0 and machine 1 in one timestep. By employing the power model presented in [13] and [14], dynamic power consumption of a processor can be modeled by x j f y , in which x j is a coefficient depending on the average switched capacitance and the activity factor of job j, f is the processor operating frequency, and y is the technology-dependent dynamic power exponent. Therefore, for each job j we have:…”
Section: B Energy Modelmentioning
confidence: 99%
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“…Therefore, the ratio between e j,0 and e j,1 for each job j needs to reflect the ratio between the dynamic energy consumption of the processor on machine 0 and machine 1 in one timestep. By employing the power model presented in [13] and [14], dynamic power consumption of a processor can be modeled by x j f y , in which x j is a coefficient depending on the average switched capacitance and the activity factor of job j, f is the processor operating frequency, and y is the technology-dependent dynamic power exponent. Therefore, for each job j we have:…”
Section: B Energy Modelmentioning
confidence: 99%
“…Using a classical energy model of a 70nm technology processor that supports 5 discrete frequencies ranging from 1 GHz to 2 GHz, whose accuracy has been verified by SPICE simulation, [13] proposes the value for y as 3.2941. Therefore, by setting f 0 = 1 GHz and f 1 = 2 GHz (the operating frequencies of our machines) and using this value for y, for each job j we have: ej,0 ej,1 = 2 3.2941 = 9.809.…”
Section: B Energy Modelmentioning
confidence: 99%
“…The resulting list is called sorted_precise_parents, which includes b tasks. Next, a subset of tasks in sorted_precise_parents is chosen such that transforming those tasks to imprecise tasks and extending the mandatory workload of their child tasks leads to the highest reduction in (10). However, instead of exploring all 2 b possible subsets, we only explore b subsets which are: the subset containing the first task in the sorted list, the subset containing the first and second tasks in the sorted list, ..., and for the b th subset, the subset containing all tasks in the sorted list.…”
Section: Determining the Number Of Processor Cycles Assigned To Optiomentioning
confidence: 99%
“…We first explain our approach for minimizing (10) for two simple task graphs that constitute base cases. Then, we explain our proposed algorithm for a general task graph.…”
Section: Determining the Number Of Processor Cycles Assigned To Optio...mentioning
confidence: 99%
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