2010
DOI: 10.1109/temc.2010.2049069
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Modeling, Quantification, and Reduction of the Impact of Uncontrolled Return Currents of Vias Transiting Multilayered Packages and Boards

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Cited by 39 publications
(16 citation statements)
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“…On the other hand, if signal vias are located away from the edges, and the package has a high count of GND vias, the cavity resonances are small, or even, negligible [8]. In this way, the boundaries due to the finite size of the cavity disappear, and the waves propagating along the cavity are not reflected.…”
Section: A Circuit Model Topologymentioning
confidence: 99%
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“…On the other hand, if signal vias are located away from the edges, and the package has a high count of GND vias, the cavity resonances are small, or even, negligible [8]. In this way, the boundaries due to the finite size of the cavity disappear, and the waves propagating along the cavity are not reflected.…”
Section: A Circuit Model Topologymentioning
confidence: 99%
“…Unfortunately, although vias play a key role in the development of reliable links, these structures are responsible for severe signal integrity problems such as impedance mismatch, crosstalk, mode conversion, and electromagnetic interference [2]. For this reason, much research effort is being dedicated to modeling [3][4][5] and reducing [6][7][8] the undesirable effects introduced by via structures in multilayer packages and PCBs. In particular, return loss and crosstalk mitigation in vias is mandatory in modern packaging technologies to avoid signal degradation because of reflections and parasitic coupling.…”
Section: Introductionmentioning
confidence: 99%
“…As shown in Figure 6, the total via capacitance consists of the via pad capacitance, via body capacitance at the inter-plane zone as well as the via capacitance above/below the interplane zones. The closed-form expressions developed in [16] were used for calculating these capacitances. These expressions are given in (2) -(4), where‫ܥ‬ ௗ , ‫ܥ‬ ௩ ௗ௬ and ‫ܥ‬ ௧/௧௧ represent the capacitances of the via pad, via body/barrel and part of via above/below the inter-plane zone.…”
Section: B Via Modelingmentioning
confidence: 99%
“…Conventional formulas found in published literature, e.g., in [16], [17], were used for the computation of the via inductance. Approximately 574 pH was obtained for the complete via, considering Cu-metallization thickness of 35 microns.…”
Section: Calculation Of Via Inductancementioning
confidence: 99%
“…One is to provide a current path by interconnecting the plane pair using either decoupling capacitors or stitching vias [2][3][4]. The other is to suppress noise propagation from the RPD location to the other parts of the system.…”
Section: Introductionmentioning
confidence: 99%