Modeling Simplification for Thermal Mechanical Analysis of High Density Chip-to-Substrate Connections

Abstract

Finite element modeling (FEM) is an important component in the design of reliable chip-to-substrate connections. However, FEM can quickly become complex as the number of input/output connections increases. Three-dimensional (3D) chip-substrate models are usually simplified where only portions of the chip-substrate structure is considered in order to conserve computer resources and time. Chip symmetry is often used to simplify the models from full-chip structures to quarter or octant models. Recently, an even simpler 3D model, general plane deformation (GPD) slice model, has been used to characterize the properties of the full-chip and local regions on the structures, such as in the structures for solder ball fatigue. In this study, the accuracy of the GPD model is examined by comparing the mechanical behavior of a flip-chip, copper pillar package from various full and partial chip models to that of the GDP model. In addition, it is shown that the GPD model can be further simplified to a half-GPD model by using the symmetry plane in the middle of the slice and choosing the proper boundary conditions. The number of nodes required for each model and the accuracy of the different FEM models are compared. Analysis of the maximum stress in the silicon chip shows that the full-chip model, quarter model, and octant model all convergence to the same result. However, the GPD and half-GPD models, with the previously used boundary conditions, converge to a different stress values from that of the full-chip models. The error in the GPD models for small, 36 I/O package was 4.7% compared to the more complete, full-chip FEM models. The displacement error in the GPD models was more than 50%, compared to the full-chip models, and increased with larger structures. The high displacement error of the GPD models was due to the ordinarily used boundary conditions which neglect the effect from adjacent I/O on the sidewall of the GPD slice. An optimization equation is proposed to account for the spatial variation in the stress on the GPD sidewall. The GPD displacement error was reduced from 50% to 3.3% for the 36 pillar array.

Fabrication and Thermo-Mechanical Characterization of Fine Pitch All-Copper Interconnect

“…The stress distribution was calculated in the copper pillar using the GPD model, as described previously. 18,20 The stress distribution along the length of the pillars and within the first 1 μm of the silicon substrate was evaluated. Figure 8 shows the maximum stress value for the pillar farthest from the center of the chip, which is the one which experienced the highest stress value as a function of misalignment.…”

“…The procedure followed previous descriptions of this modeling approach. 18,20 Recently, it has been shown that the half-GPD approach has the fewest degrees of freedom and computation time. 18 In the half-GDP model, the full chip contained a 160 × 160 array of pillars.…”

“…The modeling details are the same as described previously. 18 In this work, the modeling was extended to investigate two new aspects of pillar-to-pillar bonding using finite element analysis. The first aspect investigated was the misalignment of the pillars between the parts being joined.…”