Modeling spin transport in electrostatically-gated lateral-channel silicon devices: Role of interfacial spin relaxation

Abstract

Using a two-dimensional finite-differences scheme to model spin transport in silicon devices with lateral geometry, we simulate the effects of spin relaxation at interfacial boundaries, i.e. the exposed top surface and at an electrostatically-controlled backgate with SiO2 dielectric. These gate-voltagedependent simulations are compared to previous experimental results and show that strong spin relaxation due to extrinsic effects yield an Si/SiO2 interfacial spin lifetime of ≈ 1ns, orders of magnitude lower than lifetimes in the bulk Si, whereas relaxation at the top surface plays no substantial role. Hall effect measurements on ballistically injected electrons gated in the transport channel yield the carrier mobility directly and suggest that this reduction in spin lifetime is only partially due to enhanced interfacial momentum scattering which induces random spin flips as in the Elliott effect. Therefore, other extrinsic mechanisms such as those caused by paramagnetic defects should also be considered in order to explain the dramatic enhancement in spin relaxation at the gate interface over bulk values.

Spin Lifetime Enhancement by Shear Strain in Thin Silicon-On-Insulator Films

“…and are the spin Pauli matrices and is the -Pauli matrix in the valley degree of freedom and c is the speed of light. In the Hamiltonian [1] is the confinement potential, and the value = 1.27meVnm computed by the empirical pseudopotential method (11) is close to the one reported by Li and Dery (2).…”

Silicon spintronics: Progress and challenges

“…Primed subbands with higher subband energies originate in four in-plane valleys and are therefore four-fold degenerate, while the unprimed two-fold degenerate subbands are from the two out-of-plane valleys [97]. Despite partial degeneracy lifting in confined systems, the spin lifetime is significantly shorter in gated structures [98,99] due to the existence of the interface. Because of an ongoing shift from bulk field-effect transistors to transistors with the channel built on ultra-thin silicon-on-insulator (SOI) films and three-dimensional fin-like structures at the 22nm and more recent 14nm technology node and beyond allowing tighter confinement and thus better electrostatic control, it is expected that spin relaxation will further increase, and ways to boost the spin lifetime in SOI transistors are urgently needed.…”

“…This independently confirms the importance of f -phonon mediated intervalley scattering in bulk silicon spin relaxation. In electrically-gated lateral channel silicon systems a relatively large spin relaxation has been experimentally observed [98,99] indicating that the extrinsic interface induced spin relaxation mechanism becomes important. This may pose an obstacle in realizing spin-driven CMOS compatible devices, and a deeper understanding of fundamental spin relaxation mechanisms in silicon inversion layers, thin films, and fins is needed.…”

Spin-based devices for future microelectronics

“…However, the relatively large spin relaxation experimentally observed in electrically-gated lateral-channel silicon structures [16], [17] indicates that the extrinsic interface induced spin relaxation mechanism becomes important. This may pose an obstacle in realizing spin-driven CMOS compatible devices, and a deeper understanding of fundamental spin relaxation mechanisms in silicon inversion layers, thin films, and fins is needed.…”