Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles

Katunin, Yu. V.; Stenin, V. Ya.; Stepanov, Pavel V.

doi:10.1134/s1063739714020061

Cited by 19 publications

(4 citation statements)

References 21 publications

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“…A new method [10][11][12] of increasing the upset resilience of STG DICE triggers and memory cells is that the transistors of a DICE trigger are spaced in two groups of four transistors so that the mutually sensitive nodes are in different groups. Moreover, the connection between the two groups is just by two wires, which makes it possible to reduce the expenses for the additional area for separating the two groups.…”

Section: The Features Of the Stg Dice Memory Cell With Transistors Spmentioning

confidence: 99%

“…The simulation results of a multiple impact of a charge on the D trigger of DICE [10,11] make it possible to formulate recommendations on the mutual spacing of the N and P MOS transistors to minimize the influence of charge sharing between nodes. The transistors of one group can be arranged side-by-side, since the upset of the trigger state does not happen when the impact is applied only to this group.…”

Section: The Features Of the Stg Dice Memory Cell With Transistors Spmentioning

confidence: 99%

“…A new method for increasing the upset resilience of DICE memory cells [10][11][12] is based on the separation of all transistors of the DICE cell into two groups (Spaced Transistor Groups DICE-DICE STG) so that the impact only on one of them does not cause a upset of the logical state of the cell. Two groups of transistors are connected by only two wires, which makes it possible to increase the distance between the groups of transistors without a substantial increase in the area.…”

Section: Introductionmentioning

confidence: 99%

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Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

2016

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Abstract⎯The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE-STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32-3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55-4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.

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Section: The Features Of the Stg Dice Memory Cell With Transistors Spmentioning

confidence: 99%

Section: The Features Of the Stg Dice Memory Cell With Transistors Spmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

2016

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“…The STG DICE memory cell (Spaced Transistor Groups DICE) [7], [8] is distinguished from the DICE (Double Interlocked Cell) [9] in that its transistors are separated into two groups. The charge collection from the tracks of single nuclear particles by transistors of just one group does not lead to the cell upset.…”

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confidence: 99%