Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

Koren,; Pradhan,

doi:10.1109/tc.1987.1676906

Cited by 70 publications

(10 citation statements)

References 18 publications

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“…Increased likelihood of faults during the fabrication process results in low production yield whereas large number of active elements involved in the functional operation of the array, decreases reliability. Research efforts have been directed not only to yield improvement but also to increase fault-tolerance [KoB84,KoP87]. To increase both yield and reliability, several reconfiguration algorithms which use the available redundancy in the array have been proposed.…”

Section: Objectivesmentioning

confidence: 99%

Detailed modeling and reliability analysis of fault-tolerant processor arrays

Lopez-Benitez

Fortes²

1992

IEEE Trans. Comput.

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Recent advances in VLSI/WSI technology have led to the design of processor arrays with a large number of processing elements confined in small areas. The use of redundancy to increase fault-tolerance has the effect of reducing the ratio of area dedicated to processing elements over the area occupied by other resources in the array. The assumption of fault-free hardware support (switches, buses, interconnection links, etc.,), leads at best to conservative reliability estimates. However, detailed modeling entails not only an explosive growth in the model state space but also a difficult model construction process. To address the latter problem, a systematic method to construct Markov models for the reliability evaluation of processor arrays is proposed. This method is based on the premise that the fault behavior of a processor array can be modeled by a Stochastic Petri Net (SPN). However, in order to obtain a more compact representation, a set of attributes is associated with each transition in the Petri net model. This representation is referred to as a Modified Stochastic Petri Net (MSPN) model. A MSPN allows the construction of the corresponding Markov model as the reachability graph is being generated. The Markov model generated can include the effect of failures of several different components of the array as well as the effect of a peculiar distribution of faults when the reconfiguration occurs. Specific reconfiguration schemes such as Successive Row Elimination (SRE), Alternate Row-Column Elimination (ARCE) and Direct Reconfiguration (DR), are analyzed

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Section: Objectivesmentioning

confidence: 99%

Detailed modeling and reliability analysis of fault-tolerant processor arrays

Lopez-Benitez

Fortes²

1992

IEEE Trans. Comput.

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“…Instead, we compute the expected number of acceptable chips out of a given wafer. This yield is called the wafer-equivalent-yield [ 5 ] . The wafer-equivalentyield is defined as: …”

Section: Comparisonmentioning

confidence: 99%

Yield and layout issues in fault tolerant VLSI architectures

Upadhyaya

Chen

1991

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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“…Then, there is a need for efficient methodologies for estimating the yield and operational reliability of complex fault-tolerant systems-on-chip. When the fault-tolerant system-on-chip has a regular structure, it is often possible to make "ad-hoc" evaluations (see, for instance, [12,13,18,19]). However, many fault-tolerant designs do not have a regular structure, particularly those using a sophisticated network-on-chip as a communication subsystem among the intellectual property cores (IPs) [4].…”

Section: Introductionmentioning

confidence: 99%

Combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip

Carrasco

Suñé

2004

Microelectronics Reliability

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In this paper we develop combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip. The method for yield computation assumes that defects are produced according to a model in which defects are lethal and affect given components of the system following a distribution common to all defects; the method for the computation of operational reliability also assumes that the fault-tree function of the system is increasing. The distribution of the number of defects is arbitrary. The methods are based on the formulation of, respectively, the yield and the operational reliability as the probability that a given boolean function with multiple-valued variables has value 1. That probability is computed by analyzing a ROMDD (reduced ordered multiple-value decision diagram) representation of the function. For efficiency reasons, a coded ROBDD (reduced ordered binary decision diagram) representation of the function is built first and, then, that coded ROBDD is transformed into the ROMDD required by the methods. We present numerical experiments showing that the methods are able to cope with quite large systems in moderate CPU times. * This paper is an extended version of D.

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Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

Cited by 70 publications

References 18 publications

Detailed modeling and reliability analysis of fault-tolerant processor arrays

Detailed modeling and reliability analysis of fault-tolerant processor arrays

Yield and layout issues in fault tolerant VLSI architectures

Combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip

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