Modeling the network processor and package for power delivery analysis

This paper focuses on the power delivery network (PDN) characterization of high speed IC; particularly focusing on the on-die decoupling capacitance (Cdie) and on-die resistance and on die metal grid resistance (Rdie+Rgrid) characterization. For accurate modeling of Cdie, Rdie and Rgrid, two different measurements are studied by means of 'On-chip' and 'On package' measurement. As the 'On package' measurement approach' is a known valid approach established and relied on for many years, it is used as a benchmark to guide us in the relatively new approach of 'On chip' in order to derive the right model for Cdie/Rdie/Rgrid. As both measurement setups are different, one as a direct on-chip measurement, while the other has an additional package substrate, the paper will describe a methodology to compensate the package parasitic from the model extracted; so that the final model is a standalone Cdie/Rdie/Rgrid model without the contribution of added parasitic from the package substrate.To ensure consistency, a wafer structure which consist only the power grid structure is measured and correlated with the power grid modeling tool to confirm that both modeling methodology and measurement methodology are correlated and accurate before applying the Rgrid model. The new method has shown a good correlation to the existing method to within 95% accuracy.

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Enhanced on-Die RC Characterization Methodology

Tan

Quek

2010

2nd Asia Symposium on Quality Electronic Design (ASQED)

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System-level chip/package co-design for multi-core processors implemented with power-gating technique

Pan

Mukhopadhyay

Naeemi

2014

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems

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Based on a systemlevel design methodology and a modified power delivery network model, optimization and benchmarking are performed for a processor implemented with the powergating technique under various package configurations. Optimal widths of the sleep transistors are obtained based on how frequently the processors need to switch between active and idle state. Up to 75% of the energydelay product saving is observed for the processors using powergating technique with a low switching frequency. Additionally, the optimal position of the decap insertion is demonstrated to be application dependent.

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Switching-current measurement for multiple ICs sharing a common power island structure

Hwang

Wang

et al. 2012

2012 IEEE International Symposium on Electromagnetic Compatibility

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Switching currents in active integrated circuits (ICs) generate noise in the power distribution network (PDN), which is one of the main sources for many signal/power integrity and electromagnetic interference issues in high-speed electronic devices. Accurate knowledge of the switching currents is the key to ensure a good PDN design. This paper proposes a measurement methodology, when IC information is not available, to obtain the equivalent switching current of each IC in the case where multiple ICs are connected to a common power island structure. Time-domain oscilloscope measurements are used to capture the noise-voltage waveforms at a few locations in the power island. Combining with the multi-port frequency-domain S-parameter measurement among the same locations, an equivalent switching current for each IC is calculated. The proposed method is validated at a different location in the power island by comparing the calculated noise voltage using the equivalent switching currents as excitations with the actual measured noise voltage.

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Modeling the network processor and package for power delivery analysis

Cited by 6 publications

References 6 publications

Enhanced on-Die RC Characterization Methodology

Enhanced on-Die RC Characterization Methodology

System-level chip/package co-design for multi-core processors implemented with power-gating technique

Switching-current measurement for multiple ICs sharing a common power island structure

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