Modeling the Trade-off Between Security and Performance to Support the Product Life Cycle

Fujdiak, Radek; Blažek, Petr; Apvrille, Ludovic; Martinásek, Zdeněk; Mlýnek, Petr; Pacalet, Renaud; Smékal, David; Mrnustik, Pavel; Barabas, Maroš; Zoor, Maysam

doi:10.1109/meco.2019.8760043

Cited by 2 publications

(5 citation statements)

References 16 publications

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“…Also, we are using experience from the combined analysis of Security and Performance using SSDLC and TTool (https://ttool.telecom-paristech.fr/) applications for Interference Analysis in UC4 (Industrial drive, AQUAS project) [17].…”

Section: Methodsmentioning

confidence: 99%

Co-Engineering Gap Analysis of ANSI/ISA‑62443‑3‑3

Mlýnek

Fujdiak

Mrnustik³

et al. 2020

IJATES

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Nowadays, software and system development is a more complex process than ever was and it faces challenges, where security became one of the most crucial. Based upon co-engineering in the AQUAS project, complex standards covering development processes regarding safety, but performance and security are missing. In the paper, the representative standard for Industrial Automation and Control Systems (IACS) is selected for gap analysis, both as examples of issues in co-engineering in security and performance, and possibly for evolution and extension in security standards. For IACS, the ANSI/ISA 62443 defines procedures for implementing security requirements. Based upon co-engineering in the AQUAS project and experience from the real implementation of security by TrustPort practitioners of this domain, the paper introduces the 62443 standard gaps analysis with the goal to identify the missing part. Based on this analysis, the possible recommendations for extending 62443-3-3 are proposed.

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Section: Methodsmentioning

confidence: 99%

Co-Engineering Gap Analysis of ANSI/ISA‑62443‑3‑3

Mlýnek

Fujdiak

Mrnustik³

et al. 2020

IJATES

Self Cite

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“…Their results demonstrate a linear relation between security levels and performance. The authors of [15] propose the interaction of two tools to study the link between security requirements and their impact on performance, and help deciding high-level metrics to better capture the performance of security mechanisms. The authors are thus able to compare the performance of system models for different security levels.…”

Section: Related Workmentioning

confidence: 99%

“…To determine the computation complexity of HMAC-SHA256 (i.e. 8322 clock cycles), we have used the technique described in [15] and relying on SSDLC (Secure Software Development Life Cycle). The overhead of the message is set to 256 bits.…”

Section: System Verificationmentioning

confidence: 99%

“…To ensure the confidentiality property on the channel between PL1 and F1_3_PL1 (Req_4) encryption/decryption operators are added. We chose the AES algorithm in Cipher Block Chaining (CBC) mode and set the computational complexity to 3000 as indicated in [15].…”

Section: System Verificationmentioning

confidence: 99%

“…The computational complexity is now set to 428 cycles. This value is obtained by applying the same interaction as indicated in [15]. The security verification indicates that the confidentiality property still holds.…”

Section: System Verificationmentioning

confidence: 99%

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SysML models

Zoor

Apvrille

Pacalet

2020

Proceedings of the 23rd ACM/IEEE International Conference on Model Driven Engineering Languages and Systems: Companion Proceedi

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Designing safe, secure and efficient embedded systems implies understanding interdependencies between safety, security and performance requirements and mechanisms. In this paper, we introduce a new technique for analyzing the performance impact of safety/security implemented as hardware and software mechanisms and described in SysML models. Our analysis approach extracts a dependency graph from a SysML model. The SysML model is then simulated to obtain a list of simulation transactions. Then, to study the latency between two events of interest, we progressively taint the dependency graph according to simulation transactions and to dependencies between all software and hardware components. The simulation transactions are finally classified according to which vertex taint they correspond, and are displayed according to their timing and related hardware device. Thus a designer can easily spot which components need to be re-modeled in order to meet the performance requirement. A Rail Carriage use case studied in the scope of the H2020 AQUAS project illustrates our approach, in particular how tainting can handle the multiple occurrences of the same event. CCS CONCEPTS • Computer systems organization → Embedded software.

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Modeling the Trade-off Between Security and Performance to Support the Product Life Cycle

Cited by 2 publications

References 16 publications

Co-Engineering Gap Analysis of ANSI/ISA‑62443‑3‑3

Co-Engineering Gap Analysis of ANSI/ISA‑62443‑3‑3

SysML models

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