Modeling Time in Computing

Furia, Carlo A.; Mandrioli, Dino; Morzenti, Angelo; Rossi, Matteo

doi:10.1007/978-3-642-32332-4

Cited by 43 publications

(21 citation statements)

References 122 publications

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“…The approach exploits the metric temporal logic TRIO [6], which allows users to express timing properties of systems, including real-time ones. In fact, though in this paper we focus on the flexibility and modularity aspects of our approach rather than the real-time ones, we allow users to express and verify metric properties such as "message m1 will be followed, within 3 time units, by message m2".…”

Section: Formal Semanticsmentioning

confidence: 99%

Flexible modular formalization of UML sequence diagrams

Baresi

Kallehbasti

Rossi

2014

Proceedings of the 2nd FME Workshop on Formal Methods in Software Engineering

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UML Sequence Diagrams are one of the most commonly used type of UML diagrams in practice. Their semantics is often considered to be straightforward, but a more detailed analysis reveals diverse interpretations. These different choices must be properly supported by verification tools. This paper describes a formal framework for capturing semantic choices in a precise and modular way. The user is then able to select the semantics of interest, mix different interpretations, and analyze diagrams according to the chosen solution. This solution is supported by Corretto, our UML verification environment, to allow the user to play with different semantics and prove properties on Sequence Diagrams, accordingly.

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Section: Formal Semanticsmentioning

confidence: 99%

Flexible modular formalization of UML sequence diagrams

Baresi

Kallehbasti

Rossi

2014

Proceedings of the 2nd FME Workshop on Formal Methods in Software Engineering

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“…A signal (also called a timed state sequence) is a mapping associating nonnegative real numbers with states. Finite variability is a very common requirement for continuous-time systems, ruling out only pathological behaviors (e.g., Zeno [9]) which do not have much practical interest.…”

Section: Introductionmentioning

confidence: 99%

“…Linear Temporal Logic (LTL) is often used with this goal in the verification of finite-state models, e.g., in model checking [7]. Second, temporal logic allows a descriptive approach to specification and modeling (see, e.g., [8,9]). A descriptive model is based on axioms, written in some (temporal) logic, defining a system by means of its general properties, rather than by an operational model based on some kind of machine (e.g., a Timed Automaton) behaving in the desired way.…”

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confidence: 99%

An SMT-based approach to satisfiability checking of MITL

Bersani¹,

Rossi²,

Pietro³

2015

Information and Computation

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We present a satisfiability-preserving reduction from MITL interpreted over finitely-variable continuous behaviors to Constraint LTL over clocks, a variant of CLTL that is decidable, and for which an SMT-based bounded satisfiability checker is available. The result is a new complete and effective decision procedure for MITL. Although decision procedures for MITL already exist, the automata-based techniques they employ appear to be very difficult to realize in practice, and, to the best of our knowledge, no implementation currently exists for them. A prototype tool for MITL based on the encoding presented here has, instead, been implemented and is publicly available. IntroductionComputer systems are inherently discrete-time objects, but their application to real-time control and monitoring often requires to deal with external asynchronous events that may not always happen at integer-valued times. Hence, a discrete-time assumption requires to approximate continuous time by choosing some fixed minimal interval, thus limiting the accuracy of modeling, verification and validation of such systems. To overcome this restriction, many continuoustime models have been developed, most notably Timed Automata [4], a densetime operational model based on finite-state machines, but also descriptive models such as the continuous-time temporal logics MTL (Metric Temporal Logic) [5,6] and MITL (Metric Interval Temporal Logic) [6]. In general, the role of temporal logics in verification and validation is two-fold. First, temporal logic allows abstract, concise and convenient expression of required properties of $ This research was supported by the Programme IDEAS-ERC, Project 227977-SMScom, and by PRIN Project 2010LYA9RH. $$ Parts of this work were previously published in [1], [2] and [3], of which this article is an extension.Email addresses: marcellomaria.bersani@polimi.it (Marcello M. Bersani), matteo.rossi@polimi.it (Matteo Rossi), pierluigi.sanpietro@polimi.it (Pierluigi San Pietro) Preprint submitted to ElsevierJanuary 9, 2015 a system. Linear Temporal Logic (LTL) is often used with this goal in the verification of finite-state models, e.g., in model checking [7]. Second, temporal logic allows a descriptive approach to specification and modeling (see, e.g., [8,9]). A descriptive model is based on axioms, written in some (temporal) logic, defining a system by means of its general properties, rather than by an operational model based on some kind of machine (e.g., a Timed Automaton) behaving in the desired way. In this case, verification typically consists of satisfiability checking of the conjunction of the model and of the (negation of) its desired properties. An example of the latter approach is Bounded Satisfiability Checking (BSC) [10], where MTL specifications and properties on discrete time are translated into Boolean logic, in an approach similar to Bounded Model Checking of LTL properties of finite-state machines.In general, verification of continuous-time temporal logics is not as well supported as for discre...

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“…DES is a dynamic system with state evolution produced by the occurrence of physical events. For example, an event is opening or closing a gate in Kernel Railroad Crossing (KRC) systems [2][3]. DES can be found in domains such as manufacturing, robotic, traffic control, logistics, and communication systems, etc.…”

Section: Iintroductionmentioning

confidence: 99%

Modelling and Control of KRC Systems Using TPN and TA

Allaa¹,

Awad²,

Anwar³

et al. 2015

IJAREEIE

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This paper models and supervises kernel railroad crossing (KRC) systems using timed Petri nets and focuses on the control synthesis method, which consists in computing new firing conditions for the timed automaton (TA) transitions so that the forbidden locations are no longer reachable. The system to be modeled and supervised using timed Petri nets is converted to a TA and is analyzed using automata so that the functioning of the system respects given specifications. The main reason of using automata is that although the timed Petri nets supervisor controls the system, it fails to define the time units needed for the undefined time of a transition. Simulation results show the soundness of KRC modeling and supervision in the sense of ensuring the safety and maximizing utility (the gate should be opened as long as possible). KEYWORDS:Automata, Timed automata, discrete event systems, Petri nets, Timed Petri nets, KRC systems I.INTRODUCTIONThe process synchronization and forbidden states avoidance are considered as the main problems in both normal and abnormal modes of automation systems [1]. These characteristics allow the system to be considered as Discrete Event System (DES) and allow the researchers to perform the analysis and control of such systems using Petri nets (PN) and automata. DES is a dynamic system with state evolution produced by the occurrence of physical events. For example, an event is opening or closing a gate in Kernel Railroad Crossing (KRC) systems [2][3]. DES can be found in domains such as manufacturing, robotic, traffic control, logistics, and communication systems, etc.Important contributions in supervisory control of DES based on the Finite Automata (FA) and Petri Nets (PNs) are found in [4][5][6][7][8]. Petri net models are normally more compact than similar automata based models and are better suited for the representation of discrete event systems. They also have a good representational power [9]. On one hand, numerous approaches to the systematic construction of Petri net models have been proposed in [10]. On the other hand, because automata detail the process to be modelled, they are also employed to analysis and avoid forbidden states with ease.Historically, the theory of DES for supervision was initiated by the research work of Ramadge and Wonham [8]. A process is considered to be a spontaneous generator of events. Its functioning is characterized by event sequences. A supervisor is a DES which can modify the functioning of the process in order to avoid forbidden states. Unfortunately, the theory of Ramadge and Wonham does not a maximally permissive in nature [11]. A maximal permissive supervisor is to ensure that the controlled behaviour of the DES must be maximally permissive within a given specifications, i.e. all events which do not contradict the given specifications are allowed to happen. Thus, the theory of Ramadge and Wonham cannot be used to control all DES. An extension of this theory to the control of DES is proposed to force the occurrence of certain events to...

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Modeling Time in Computing

Cited by 43 publications

References 122 publications

Flexible modular formalization of UML sequence diagrams

Flexible modular formalization of UML sequence diagrams

An SMT-based approach to satisfiability checking of MITL

Modelling and Control of KRC Systems Using TPN and TA

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