Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

Saheb, Zina; El-Masry, E.I.

doi:10.1007/s10470-015-0553-8

Cited by 9 publications

(3 citation statements)

References 6 publications

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“…Direct tunneling occurs mainly due to the electrons and holes tunneling, the electron tunnel from the conduction band and the valence band while the holes tunnel from valence band. It is more sensitive to the gate oxide thickness [51]. The …”

Section: Gate Tunneling Currentmentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

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Section: Gate Tunneling Currentmentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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“…In recent years, the industry has demanded the scaling down of semiconductor devices to satisfy the three key requirements including high density, rapid speed, and low power [7][8][9][10][11]. However, for the specific 65 nm process, the limitation of the tunnel oxide layer thickness, which is one of the most critical parameters of the device, is 9 nm which would not decrease to follow the scaling trend [12,13].…”

Section: Introductionmentioning

confidence: 99%

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

Cong,

Hoang

2024

Modelling and Simulation in Engineering

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Floating-gate transistor lies at the heart of many aspects of semiconductor applications such as neural networks, analog mixed-signal, neuromorphic computing, and especially in nonvolatile memories. The purpose of this paper was to design a high-performance nanocrystal floating-gate transistor in terms of a large memory window, low power, and extraordinary erasing speeds. Besides, the transistor achieves a thin thickness of the tunnel gate oxide layer. In order to obtain the high-performance design, this work proposed a set of structure parameters for the device such as the tunnel oxide layer thickness, Interpoly Dielectric (IPD), dot dimension, and dot spacing. Besides, this work was successful in the virtual fabrication process and methodology to fabricate and characterize the 65 nm nanocrystal floating-gate transistor. Regarding the results, while the fabrication process solves the limitation of the tunnel oxide layer thickness with the small value of 6 nm, the performance of the transistor has been significantly improved, such as 2.8 V of the memory window with the supply voltage of ±6 V at the control gate. In addition, the operation speeds are compatible, especially the rapid erasing speeds of 2.03 μs, 28.6 ns, and 1.6 ns when the low control gate voltages are ±9 V, ±12 V, and ±15 V, respectively.

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“…The ongoing drive to miniaturize electronic devices has led to issues regarding reliability due to the increased leakage of current by direct tunneling [1]. To solve this problem, high-k materials having wide band gaps and high dielectric constants, such as Al 2 O 3 , Y 2 O 3 , HfO 2 , and ZrO 2 , are used [2].…”

Section: Introductionmentioning

confidence: 99%

Thermal Decomposition In Situ Monitoring System of the Gas Phase Cyclopentadienyl Tris(dimethylamino) Zirconium (CpZr(NMe2)3) Based on FT-IR and QMS for Atomic Layer Deposition

Choi

Shim

et al. 2020

Nanoscale Res Lett

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We developed a newly designed system based on in situ monitoring with Fourier transform infrared (FT-IR) spectroscopy and quadrupole mass spectrometry (QMS) for understanding decomposition mechanism and byproducts of vaporized Cyclopentadienyl Tris(dimethylamino) Zirconium (CpZr(NMe 2) 3) during the move to process chamber at various temperatures because thermal decomposition products of unwanted precursors can affect process reliability. The FT-IR data show that the-CH 3 peak intensity decreases while the-CH 2and C=N peak intensities increase as the temperature is increased from 100 to 250°C. This result is attributed to decomposition of the dimethylamido ligands. Based on the FT-IR data, it can also be assumed that a new decomposition product is formation at 250°C. While in situ QMS analysis demonstrates that vaporized CpZr(NMe 2) 3 decomposes to Nethylmethanimine rather than methylmethyleneimine. The in situ monitoring with FT-IR spectroscopy and QMS provides useful information for understanding the behavior and decomposes of CpZr(NMe 2) 3 in the gas phase, which was not proven before. The study to understand the decomposition of vaporized precursor is the first attempt and can be provided as useful information for improving the reliability of a high-advanced ultra-thin film deposition process using atomic layer deposition in the future.

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Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

Cited by 9 publications

References 6 publications

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

Thermal Decomposition In Situ Monitoring System of the Gas Phase Cyclopentadienyl Tris(dimethylamino) Zirconium (CpZr(NMe2)3) Based on FT-IR and QMS for Atomic Layer Deposition

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