Modelling of the hole mobility in p-channel MOS transistors fabricated on (1 1 0) oriented silicon wafers

Gaubert, Philippe; Teramoto, Akinobu; Ohmi, Tadahiro

doi:10.1016/j.sse.2009.11.004

Cited by 19 publications

(13 citation statements)

References 27 publications

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“…Moreover, the large confinement effective mass of the p-type Si(110) surface make the (110)/[110] Si channel an ideal candidate for thermoelectric applications [32]. Therefore, the controlled assembly of C 60 molecules into perfectly ordered parallel molecular NW arrays on Si(110) offers an opportunity for the rational nanofabrication of advanced organic nanomaterials with potential applications in future multifunctional Si-based molecular nanoelectronics that will combine the well-established CMOS technology [29][30][31] with the exotic physical and chemical properties of C 60 molecules [1][2][3][4][5][6].…”

mentioning

confidence: 99%

Large area self-ordered parallel C60 molecular nanowire arrays on Si(110) surfaces

Hong

Gao

2016

Carbon

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mentioning

confidence: 99%

Large area self-ordered parallel C60 molecular nanowire arrays on Si(110) surfaces

Hong

Gao

2016

Carbon

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“…Assuming that the effective electric field E eff is proportional to the gate overdrive voltage V g -V th , the dependence of the several scattering mechanisms can be introduced into Eq. (9), which is already modeling the Coulomb scatterings mechanisms to finally give [21] …”

Section: Silicon Wafers With a (110) Crystallographic Orientationmentioning

confidence: 99%

“…Indeed, the hole mobility in Si (110) wafers has a peculiar behavior in the form of the inter-subband phonon scatterings. Contrary to the acoustic phonon scatterings that are more and more limiting the mobility with an increase of the effective electric field, the inter-subband phonon scatterings have the specificity to decrease when the effective electric field is increased [21,28] as sketched in Figure 5.…”

Section: Silicon Wafers With a (110) Crystallographic Orientationmentioning

confidence: 99%

Carrier Mobility in Field-Effect Transistors

Gaubert¹,

Teramoto²

2017

Different Types of Field-Effect Transistors - Theory and Applications

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Authors investigate the carrier mobility in field-effect transistors mainly when fabricated on Si(110) wafers. They showed that the methods developed to extract the conduction parameters cannot be implemented for Si(110) p-MOSFETs. Authors then developed a more accurate mobility model able to simulate not only the drivability but also the transconductance for these same devices. The study of the relation between the mobility, channel direction and wafer orientation revealed that the channel direction had a significant impact on the mobility for transistors fabricated on Si(110) wafers, the highest electron and hole mobilites being obtained for a channel along the <100> and <110> directions, respectively. No relations were found for Si(100) wafers. The study of the dependence of the scattering mechanism limiting the mobility in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms were responsible for the degradation of the mobility when compared to the one on Si(100) wafers. Finally, the measurement of the mobility in an accumulation-mode MOSFETs is not straightforward since a bulk contribution, owing to the SOI layer, is adding to channel current. A methodology has been successfully implemented that led to the experimental verification of the universal behaviour of the mobility in an accumulation layer.

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“…where W and L are the effective channel width and length respectively, C ox is the gate oxide capacitance, V d,s is the drain-source voltage, R p is the parasitic resistance at source and drain contacts and µ eff is the effective mobility given as [19] …”

Section: Numerical Tests With Mosfetmentioning

confidence: 99%

On Estimating Differential Conductance from Noisy I-V Measurements in Delineating Device Parameters

Roy¹

2017

AEI

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Differential conductance is a key to characterizing a solid-state device. Estimation of differential conductance from current-voltage characteristic curve amounts to estimate the first order derivative from a discrete set of current-voltage measurements of the device under test. Conventional difference method in estimating derivative is inadequate when data contain noise. A robust method of estimating the first order derivative from a discrete set of evenly distributed current versus voltage measurements is designed where the method does not pose any constraints or limits on the data interval. The proposed method is formalized in the premise of the fundamental theorem of calculus and the inverse problem. The robustness of estimation is ensured using a regularization technique where the regularization operator is considered as a first order differential operator. A modified form of the L-curve technique is used to determine an optimal regularization parameter. The method is tested on synthetic and measured current-voltage characteristics of Schottky diode and MOSFET.

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Modelling of the hole mobility in p-channel MOS transistors fabricated on (1 1 0) oriented silicon wafers

Cited by 19 publications

References 27 publications

Large area self-ordered parallel C60 molecular nanowire arrays on Si(110) surfaces

Large area self-ordered parallel C60 molecular nanowire arrays on Si(110) surfaces

Carrier Mobility in Field-Effect Transistors

On Estimating Differential Conductance from Noisy I-V Measurements in Delineating Device Parameters

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