Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

Bajura, Michael; Boulghassoul, Y.; Naseer, R.; DasGupta, Sandeepan; Witulski, A.F.; Sondeen, J.; Stansberry, Scott D.; Draper, J.; Massengill, L.W.; Damoulakis, J. N.

doi:10.1109/tns.2007.892119

Cited by 89 publications

(30 citation statements)

References 33 publications

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“…The same might not apply to the rest of bits within a real system. As reported by [22], the probability of not upsetting during a time t can be modeled by the 0th order Poisson distribution. Thus, it can be expressed as:…”

Section: Motivationmentioning

confidence: 99%

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Martínez-Álvarez

Restrepo-Calle

Cuenca-Asensi

et al. 2016

IEEE Trans. Dependable and Secure Comput.

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Abstract-Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.

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Section: Motivationmentioning

confidence: 99%

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Martínez-Álvarez

Restrepo-Calle

Cuenca-Asensi

et al. 2016

IEEE Trans. Dependable and Secure Comput.

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“…Bajura et al; represented the hardening approach to reduce the soft error rates [2]. Two approach of hardening is given which are critical circuit based hardening and system based hardening.…”

Section: Literature Surveymentioning

confidence: 99%

A Brief Review on Soft Errors and LDPC Codes

2016

IJSR

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Abstract:In current scenario, due to high demand of technology scaling and higher integration density, the designers are using nanodevices for computer system and other memory system. Despite having many advantages such as lower area overhead and lower power consumption, these devices has major disadvantage that they are more prone to soft errors. Due to this reason the reliability of these systems are severely affected. Many error detection and correction codes have been studied to reduce this error. There are vast classes of such codes; some of them are hamming codes, turbo codes, BCH codes and LDPC codes. But among these codes LDPC codes achieve better performance and lower decoding complexity. LDPC codes were originally discovered by Robert G. Gallager. But after the rediscovery of LDPC codes by Mackay and Neal in 1995 interest on LDPC codes increases because of its bit error performance approaches asymptotically the Shannon limit. An LDPC code is a special class of linear block codes whose parity-check matrix H has low density of one's i.e. sparse. Due to this sparsity in LDPC codes there is low complexity decoding and its implementation is also simple. Also LDPC codes provides large degree of parallelism that can be exploited in the decoder and in LDPC codes information block length are long enough. In addition LDPC codes provides wide range of trade-offs between performance and complexity. LDPC codes find its application in many areas such as satellite transmission of digital television. LDPC codes are also used for 10GBase-T Ethernet that transmits data at 10 gigabits per second over twisted pair cable.

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“…Due to consequence of higher integration densities, there is an increase in soft errors which points the need for more error correction capabilities [1], [3]. Therefore, it has become conventional to safeguard memories with the application of error correcting codes (ECC) like single-error-correcting (SEC) Hamming code, single-error-correcting double-error-detecting (SEC-DED) extended-Hamming, or SEC-DED Hsiao codes With multi-bit upsets (MBU) becoming a major contributor to soft errors.…”

Section: Introductionmentioning

confidence: 99%