Modified dynamic current mode logic based LFSR for low power applications

Babu, A. Suresh; Anand, B.

doi:10.1016/j.micpro.2019.102945

Cited by 13 publications

(3 citation statements)

References 5 publications

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“…The observed number of in are indicated 's where . E= be the expected value of the event , distributed as chi-square distribution with one of freedom's degree [15].  Serial Test: This test's objective is to determine whether the frequency of as a subsequence is close to the expected value for a random sequence:…”

Section: Randomness Criterionmentioning

confidence: 99%

Design of New Efficient Stream Key Generator to Protect the Classified Information

Abed,

Nasir

2024

Iraqi Journal of Science

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In this paper, we will create a new stream key cipher generator (KG) that is based on the LFSR unit and a chaotic map. The created KG can be used for a variety of purposes, including cryptography and steganography. The suggested KG is called Efficient Stream KG, and it demonstrates its efficiency when it passes all of the basic efficiency criteria tests, namely the periodicity, linear complexity, correlation immunity, and randomness.

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Section: Randomness Criterionmentioning

confidence: 99%

Design of New Efficient Stream Key Generator to Protect the Classified Information

Abed,

Nasir

2024

Iraqi Journal of Science

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“…The process of switching required more time. A modified dynamic current mode logic that makes use of the LFSR circuit's power usage was created by Suresh Babu and colleagues [9]. The downside of [8] is lessened by this design.…”

Section: Development Processmentioning

confidence: 99%

High-performance LFSR circuit design based on XOR gates

Xiao

2023

J. Phys.: Conf. Ser.

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The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

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“…The extraordinary advancements in optical components and devices in current years have resulted in major efforts in implementing optical signal processing methods. LFSR played an important role in classical electronics, such as circuits that generate encryption and decryption, pseudorandom binary sequence (PRBS), and a bit error rate measuring system [3], [4]. Optical LFSRs, which have the advantage of speed, are predicted to provide benefits in similar types of applications.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable linear feedback shift register for wireless communication and coding

Devrari

Kumar

2023

IJRES

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<p>Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.</p>

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Modified dynamic current mode logic based LFSR for low power applications

Cited by 13 publications

References 5 publications

Design of New Efficient Stream Key Generator to Protect the Classified Information

Design of New Efficient Stream Key Generator to Protect the Classified Information

High-performance LFSR circuit design based on XOR gates

Reconfigurable linear feedback shift register for wireless communication and coding

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