Modified Floating Gate and IPD Profile for Better Cell Performance of Sub-50 nm NAND Flash Memory

Abstract

y = -0.0857x 2 + 0.8761x + 0.0414 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 O dose(1E15/cm^2) Oxide thk(nm) Figure 1. Oxide thickness formed on the top of poly after 15 second anneal at 950°C vs. oxygen implant dose. Oxygen implant energy was 1KeV. Oxide thickness was measured by ARXPS.Abstract-We report a new approach to utilize oxygen implantation on the top of the floating gate (FG) to improve the cell performance of a sub-50 nm NAND flash memory cell. This method was used to form a thin oxide layer only on the top of the FG but not on the sidewalls. It also rounded the corners of the FG. As a result, the leakage current between FG and control gate (CG) was reduced without sacrificing the gate coupling ratio (GCR). With this approach we improved V t_sat_program and V t_sat_erase without degrading V g V t_program and V g V t_erase on real Si.