Modified Genetic Algorithm Based Method on Low-Power Mapping in Network-on-chip

Dai, Qi-hua; Liu, Qin-rang; Shen, Jian; Sun, Miao

doi:10.2991/asei-15.2015.366

Cited by 2 publications

(1 citation statement)

References 10 publications

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“…In the 3D NoC mapping, the population individuals are coded by integers, assuming that the individual X = (x1, x2,..., xn), n is the number of IP cores of the TCG, and xi is the number of the IP core. The code of individual X is a sequence from 1 to n, and a mapping scheme can be obtained by decoding the code of individual X [23].…”

Section: Population Individual Vector Representationmentioning

confidence: 99%

3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

2021

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Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an improved algorithm based on genetic algorithm on how to properly map IP (Intellectual Property) cores to 3D NoC. First, in view of the randomness of the traditional genetic algorithm in individual selection, an improved greedy algorithm is used in the initial population generation stage to make the generated individuals reach the optimal. Secondly, in view of the weak local optimization ability of the traditional genetic algorithm and prone to premature problems, the simulated annealing algorithm is added in the crossover operation stage to make the offspring reach the global optimum. The experimental results show that compared with the traditional genetic algorithm, the algorithm has better convergence and low power consumption performance, which can quickly search for a better solution, in the case of a large number of cores (124 IP cores), the average power consumption can be reduced by 42.2%.

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Section: Population Individual Vector Representationmentioning

confidence: 99%

3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

2021

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A high-level simulator for Network-on-Chip

Paris,

Pedrino

2024

Integrated Computer-Aided Engineering

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This study presents a high-level simulator for Network-on-Chip (NoC), designed for many-core architectures, and integrated with the PlatEMO platform. The motivation for developing this tool arose from the need to evaluate the behavior of application mapping algorithms and the routing, both aspects are essential in the implementation and design of NoC architectures. This analysis underscored the importance of having effective NoC simulators as tools that allow for studying and comparing various network technologies while ensuring a controlled simulation environment. During this investigation and evaluation, some simulators, such as Noxim, NoCTweak, and NoCmap, among others, offered configurable parameters for application traffic, options to synthetically define topology and packet traffic patterns. Additionally, they include mapping options that optimize latency and energy consumption, routing algorithms, technological settings such as the CMOS process, and measurement options for evaluating performance metrics such as throughput and power usage. However, while these simulators meet detailed technical demands, they are mostly restricted to analyzing the low-level elements of the architecture, thus hindering quick and easy under- standing for non-specialists. This insight underscored the challenge in developing a tool that balances detailed analysis with a comprehensive learning perspective, considering the specific restrictions of each simulator analyzed. Experiments demonstrated the proposed simulator efficacy in handling algorithms like GA, PSO, and SA variant, and, surprisingly, revealed limitations of the XY algorithm in Mesh topologies, indicating the need for further investigation to confirm these findings. Future work will expand the simulator functionalities, incorporating a broader range of algorithms and performance metrics, to establish it as an indispensable tool for research and development in NoCs.

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Modified Genetic Algorithm Based Method on Low-Power Mapping in Network-on-chip

Cited by 2 publications

References 10 publications

3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

A high-level simulator for Network-on-Chip

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