Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Abstract

Network on chip (NoC) has been proposed as an enormously scalable solution to address communication problems in system on chip (SoC). The interconnections among multiple cores/multiple Intellectual Property modules on a chip have a major impact on communication and performance of the chip design in terms of area, throughput, latency and power. Hence, an efficient design of the NoC interconnect is of paramount importance. In this study, a novel idea of the NoC router using a singleside buffer in the input block and a programmable priority encoder in the scheduler is discussed and a 4 × 4 mesh topology based router design is implemented on a field programmable gate array device using these blocks. This gives an area optimisation of the router due to the use of a small buffer. Furthermore, a modified X-Y routing algorithm is discussed and implemented for the 8 × 8 mesh topology-based router. The result shows that the modified X-Y routing algorithm requires only two hops to reach any source destination pair resulting in latency optimisation of the NoC router. Thus, the router design with a single buffer and a modified X-Y routing algorithm provides the best solution for area and latency optimisation.

Design of fault tolerant algorithm for network on chip router using field programmable gate array

“…Figure 1. Architecture of single node router [24] This single node architecture accepts a 24-bit input data packet along with clk and reset signals. The 24-bit input data can be split into 16-bits of information, along with 4-bit source address and 4-bit destination address and the output data consists of 24-bits of data received at the end of a successful cycle of data transfer.…”

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

“…This increases the significance of implementing a reliable and highly efficient communication architecture that takes sufficient care of these packets unless delivered. For such communication-intensive architectures, traditional communication methodologies such as bus-based interconnection or point-to-point interconnection becomes less feasible because of lack of proper scalability (Shahane and Pisharoty, 2019) and performance improvement chances (Phing et al, 2016;Debbarma and Debbarma, 2017). Analyzing the requirements of such advanced systems, a high performance, reusable and scalable NoC can be a promising solution (Jain et al, 2015).…”