Modified LRU policies for improving second-level cache behavior

Wong, Wayne A.; Baer, Jean-Loup

doi:10.1109/hpca.2000.824338

Cited by 67 publications

(62 citation statements)

References 17 publications

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“…Second, the line is re-referenced at a distance greater than the cache size, which causes the LRU policy to evict the line before it gets reused. Several studies have investigated bypassing [10][3] [6] [19] and early eviction [21][20] of lines with poor temporal locality. However, temporal locality exploited by the cache is a function of both the replacement policy and the size of the working set relative to the available cache size.…”

Section: Motivationmentioning

confidence: 99%

Adaptive insertion policies for high performance caching

Qureshi

Jaleel

Patt

et al. 2007

SIGARCH Comput. Archit. News

213

216

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The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applications, the majority of lines traverse from the MRU position to the LRU position without receiving any cache hits, resulting in inefficient use of cache space. Cache performance can be improved if some fraction of the working set is retained in the cache so that at least that fraction of the working set can contribute to cache hits.We show that simple changes to the insertion policy can significantly reduce cache misses for memory-intensive workloads. We propose the LRU Insertion Policy (LIP) which places the incoming line in the LRU position instead of the MRU position. LIP protects the cache from thrashing and results in close to optimal hitrate for applications that have a cyclic reference pattern. We also propose the Bimodal Insertion Policy (BIP) as an enhancement of LIP that adapts to changes in the working set while maintaining the thrashing protection of LIP. We finally propose a Dynamic Insertion Policy (DIP) to choose between BIP and the traditional LRU policy depending on which policy incurs fewer misses. The proposed insertion policies do not require any change to the existing cache structure, are trivial to implement, and have a storage requirement of less than two bytes. We show that DIP reduces the average MPKI of the baseline 1MB 16-way L2 cache by 21%, bridging two-thirds of the gap between LRU and OPT.

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Section: Motivationmentioning

confidence: 99%

Adaptive insertion policies for high performance caching

Qureshi

Jaleel

Patt

et al. 2007

SIGARCH Comput. Archit. News

213

216

View full text Add to dashboard Cite

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“…We want to see exactly how much space there is for improvement for each specific benchmark and cache configuration. Related work does give some answers [14], but the results differ and usually just the average value is given.…”

Section: Cache Replacement Questionsmentioning

confidence: 99%

“…There have been some efforts to further improve cache replacement decisions, for example using the compiler [13] or hardware/software techniques [14].…”

Section: Introductionmentioning

confidence: 99%

Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

Al-Zoubi

Milenković

2004

Proceedings of the 42nd Annual Southeast Regional Conference

105

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Replacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches. The state-of-the-art processors employ various policies such as Random, Least Recently Used (LRU), Round-Robin, and PLRU (Pseudo LRU), indicating that there is no common wisdom about the best one. Optimal yet unattainable policy would replace cache memory block whose next reference is the farthest away in the future, among all memory blocks present in the set.In our quest for replacement policy as close to optimal as possible, we thoroughly explored the design space of existing replacement mechanisms using SimpleScalar toolset and SPEC CPU2000 benchmark suite, across wide range of cache sizes and organizations. In order to better understand the behavior of different policies, we introduced new measures, such as cumulative distribution of cache hits in the LRU stack. We also dynamically monitored the number of cache misses, per each 100000 instructions.Our results show that the PLRU techniques can approximate and even outperform LRU with much lower complexity, for a wide range of cache organizations. However, a relatively large gap between LRU and optimal replacement policy, of up to 50%, indicates that new research aimed to close the gap is necessary. The cumulative distribution of cache hits in the LRU stack indicates a very good potential for way prediction using LRU information, since the percentage of hits to the bottom of the LRU stack is relatively high.

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“…Wong and Bauer [14] modified the standard LRU to maintain data that exhibited higher temporal locality. Alghazo et al [15] proposed a mechanism called SF-LRU (Second-Chance Frequency LRU).…”

Section: Related Workmentioning

confidence: 99%

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Lira

Molina

González³

2009

2009 IEEE International Conference on Computer Design

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Abstract-The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. Non Uniform Cache Architectures (NUCA) have been introduced to deal with this problem. This memory organization divides the whole memory space into smaller pieces or banks allowing nearer banks to have better access latencies than further banks. Moreover, an adaptive replacement policy that efficiently reduces misses in the last-level cache could boost performance, particularly if set associativity is adopted. Unfortunately, traditional replacement policies do not behave properly as they were designed for single-processors. This paper focuses on Bank Replacement. This policy involves three key decisions when there is a miss: where to place a data block within the cache set, which data to evict from the cache set and finally, where to place the evicted data. We propose a novel replacement technique that enables more intelligent replacement decisions to be taken. This technique is based on the observation that some types of data are less commonly accessed depending on which bank they reside in. We call this technique LRU-PEA (Least Recently Used with a Priority Eviction Approach). We show that the proposed technique significantly reduces the requests to the off-chip memory by increasing the hit ratio in the NUCA cache. This translates into an average IPC improvement of 8% and into an Energy per Instruction (EPI) reduction of 5%.

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Modified LRU policies for improving second-level cache behavior

Cited by 67 publications

References 17 publications

Adaptive insertion policies for high performance caching

Adaptive insertion policies for high performance caching

Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

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