Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network

Abstract

Biologically-inspired packet switched network on chip (NoC) based hardware spiking neural network (SNN) architectures have been proposed as an embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in SNNs require large distributed on-chip memory, which poses serious challenges for compact hardware implementation of such architectures. Based on the structured neural organisation observed in human brain, a modular neural networks (MNN) design strategy partitions complex application tasks into smaller subtasks executing on distinct neural network modules, and integrates intermediate outputs in higher level functions. This paper proposes a hardware modular neural tile (MNT) architecture that reduces the SNN topology memory requirement of NoC-based hardware SNNs by using a combination of fixed and configurable synaptic connections. The proposed MNT contains a 16:16 fully-connected feed-forward SNN structure and integrates in a mesh topology NoC communication infrastructure. The SNN topology memory requirement is 50 % of the monolithic NoC-based hardware SNN implementation. The paper also presents a lookup table based SNN topology memory allocation technique, which further increases the memory utilisation efficiency. Overall the area requirement of the architecture is reduced by an average of 66 % for practical SNN application topologies. The paper presents micro-architecture details of the proposed MNT and digital neuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65 nm low-power CMOS technology. The evolvable capability of the proposed MNT and its suitability for executing subtasks within a MNN execution architecture is demonstrated by successfully evolving benchmark SNN application tasks representing classification and non-linear control functions. The paper

Fixed latency on-chip interconnect for hardware spiking neural network architectures

“…A Modular Neural Tile (MNT) architecture has been proposed for reducing the silicon area, by using a combination of fixed and configurable synaptic connections [12]. The proposed MNT comprises a 16:16 neuron fully connected SNN.…”

“…The reported EMBRACE hardware modular SNN architecture illustrated in figure 1, uses a packet switched NoC for synaptic connectivity between Modular Neural Tiles (MNT) [10] [12]. Routers are connected in North, East, South and West directions, forming a manhattan-style, two dimensional mesh topology NoC architecture.…”

“…This technique offers practical implementation by allowing a sampling time window of a few milliseconds, required by real-life embedded applications. The EMBRACE architecture prototyped on Xilinx FPGA has been successfully applied to benchmark SNN control and classifier applications (such as pole balancer, two-input XOR and Wisconsin cancer dataset classifier) using spike rate coding [9] [11] [12]. The packet switched NoC uses shared buffering and physical channel resources to support a large number of virtual synaptic connections in the EMBRACE architecture.…”

“…Practical SNN systems use spike rates that are much lower than the system clock frequency. Assuming the SNN application spike rate encoding requirement is 1024 spikes in a STW of 1ms, the maximum spike injection rate is one spike in 196 clock cycles for the system clock frequency of 200Mhz [9] [12]. Also, increase in the system clock frequency results in slower spike rates for the given encoding resolution.…”

“…The NoC based synaptic connectivity approach provides flexible inter-neuron communication channels, scalable interconnect and connection reconfigurability [8] [9]. The authors have investigated and proposed EMBRACE 1 as an embedded computing element for implementation of large scale SNNs [10] [11] [12]. The proposed EMBRACE mixed-signal architecture incorporates neuron circuits interconnected using a packet switched NoC architecture.…”