Modular Partitioning for Incremental Compilation

Dehkordi, Mehrdad Eslami; Brown, Stephen D.; Borer, Terry

doi:10.1109/fpl.2006.311202

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…(iii) The CAD tool could use the location of the multi-local logic to automatically partition its enclosing modules, automating the approach we used throughout this paper. Some prior work by Dehkordi, Brown, and Borer has explored this kind of automated modular partitioning, but only to control incremental recompilation time, with no impact on frequency [23].…”

Section: Further Workmentioning

confidence: 98%

Maximizing speed and density of tiled FPGA overlays via partitioning

LaForest

Steffan

2013

2013 International Conference on Field-Programmable Technology (FPT)

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Common practice for large FPGA design projects is to divide sub-projects into separate synthesis partitions to allow incremental recompilation as each sub-project evolves. In contrast, smaller design projects avoid partitioning to give the CAD tool the freedom to perform as many global optimizations as possible, knowing that the optimizations normally improve performance and possibly area. In this paper, we show that for high-speed tiled designs composed of duplicated components and hence having multi-localities (multiple instances of equivalent logic), a designer can use partitioning to preserve multi-locality and improve performance. In particular, we focus on the lanes of SIMD soft processors and multicore meshes composed of them, as compiled by Quartus 12.1 targeting a Stratix IV EP4SE230F29C2 device. We demonstrate that, with negligible impact on compile time (less than ±10%): (i) we can use partitioning to provide high-level information to the CAD tool about preserving multi-localities in a design, without low-level micro-managing of the design description or CAD tool settings; (ii) by preserving multi-localities within SIMD soft processors, we can increase both frequency (by up to 31%) and compute density (by up to 15%); (iii) partitioning improves the density and speed (by up to 51 and 54%) of a mesh of soft processors, across many building block configurations and mesh geometries; (iv) the improvements from partitioning increase as the number of tiled computing elements (SIMD lanes or mesh nodes) increases. As an example of the benefits of partitioning, a mesh of 102 scalar soft processors improves its operating frequency from 284 up to 437 MHz, its peak performance from 28,968 up to 44,574 MIPS, while increasing its logic area by only 0.85%.

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Section: Further Workmentioning

confidence: 98%

Maximizing speed and density of tiled FPGA overlays via partitioning

LaForest

Steffan

2013

2013 International Conference on Field-Programmable Technology (FPT)

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“…An interactive synthesis flow was first proposed almost 30 years ago [8], motivated to improve timing closure in digital design. The authors claim that the flow needed under 30 minutes to evaluate relatively large designs (for the time), but could compute the effects in frequency of a small design change in only a few seconds of CPU time.…”

Section: Related Workmentioning

confidence: 99%

LiveSynth

Possignolo

Renau

2017

Proceedings of the 54th Annual Design Automation Conference 2017

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Currently, one of the major bottlenecks in digital design is synthesis. Each iteration of a design takes several hours to synthesize, putting pressure on designers to carefully consider when to submit jobs and wait for the delayed feedback. This delay is especially important in FPGA emulation, when synthesis is performed frequently while fixing the system functionality. This work proposes LiveSynth, a different approach for digital design with relatively quick feedback after small, incremental changes. Our approach delivers results with close-to-optimal quality-within a few seconds of processing time in most cases. LiveSynth was able to improve synthesis time by about 10x with minimal impact on QoR.

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Modular Partitioning for Incremental Compilation

Cited by 2 publications

References 8 publications

Maximizing speed and density of tiled FPGA overlays via partitioning

Maximizing speed and density of tiled FPGA overlays via partitioning

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