Modular reduction by multi-level table lookup

Parhami, Behrooz

doi:10.1109/mwscas.1997.666114

Cited by 10 publications

(5 citation statements)

References 12 publications

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“…This property can significantly increase the reliability and performance of devices for constructing integers. This is achieved both due to the low-bitness (low-digit) construction of devices for raising integers, and due to the possibility of using (unlike PNS) tabular arithmetic [28], where the arithmetic operations of addition, subtraction and multiplication are performed almost in one machine cycle. In particular, the low-bitness of the residues in the representation of numbers in the SRC makes it possible to choose a wide range of options for system engineering solutions when implementing modular arithmetic operations based on the following principles [29]: the summation principle (based on the use of low-bit binary modulo adders) [30]; tabular principle (based on the use of permanent storage devices of small sizes) [31]; the principle of ring shift(based on the use of ring shift registers) [32].This circumstance makes it possible to implement a device for raising integers to an arbitrary power modulo e  SRC of low-bitness (low-digit capacity).…”

Section: Discussionmentioning

confidence: 99%

Mathematical Model of the Process of Raising Integers to an Arbitrary Power of a Natural Number in the System of Residual Classes

Yanko,

Kovalchuk

2023

TACS

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It is known that the use of a non-positional number system in residual classes (SRC) in computer systems (CS) can significantly increase the speed of the implementation of integer arithmetic operations. The use of such properties of a non-positional number system in the SRC as independence, equality and low-bitness (low-digit capacity) of the residues that define the non-positional code data structure of the SRC provides high user performance for the implementation in the CS of computational algorithms consisting of a set of arithmetic (modular) operations. The greatest efficiency from the use of the SRC is achieved when the implemented algorithms consist of a set of arithmetic operations such as addition, multiplication and subtraction. There is a large class of algorithms and tasks (tasks of implementing cryptoalgorithms, optimization tasks, computational tasks of large dimension, etc.), where, in addition to performing integer arithmetic operations of addition, subtraction, multiplication, raising integers modulo and others in a positive numerical range, there is a need to implement the listed above arithmetic and other operations, in the negative numerical range. The need to perform these operations in a negative numerical range significantly reduces the overall efficiency of using the SRC as a number system of the CS. In this aspect, the lack of a mathematical model for the process of raising integers in the SRC in the negative numerical region makes it difficult to develop methods and procedures for raising integers to an arbitrary power of a natural number in the SRC, both in positive and negative numerical ranges. The purpose of the article is the synthesis of a mathematical model of the process of raising integers to an arbitrary power of a natural number in the SRC, both in positive and negative numerical ranges.

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Section: Discussionmentioning

confidence: 99%

Mathematical Model of the Process of Raising Integers to an Arbitrary Power of a Natural Number in the System of Residual Classes

Yanko,

Kovalchuk

2023

TACS

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“…As evident from Table I and discussion of the examples it contains, redundant residue sets have been applied in an ad hoc fashion as tools for speeding up or simplifying circuit realizations 3,8,11,12,16,19 . Only very recently have these been explicitly recognized as redundant residues and, thus, received a unified treatment 14 .…”

Section: Consider a Modulus M Satisfyingmentioning

confidence: 99%

Application of symmetric redundant residues for fast and reliable arithmetic

Parhami

2002

SPIE Proceedings

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Despite difficulties in general division, magnitude comparison, and sign detection, residue number system arithmetic has been used for many special-purpose systems in light of its parallelism and modularity for the most common arithmetic operations of addition/subtraction and multiplication. Computation in RNS requires modular reduction, both for the initial conversion from binary to RNS and after each operation to bring the result back to within a valid residue range. Use of redundant residues simplifies this critical operation, leading to even faster arithmetic. One type of redundant mod-m residue, that keeps the representational redundancy to the minimum of 1 bit per residue, has the nearly symmetric range [-m, m) and allows two values for each pseudoresidue: 〈x〉 m or 〈x〉 m -m. We study the extent of simplification and speed-up in the modular reduction process afforded by such redundant residues and discuss its potential implications to the design of RNS arithmetic circuits. In particular, we show that besides cost and performance benefits, introduction of error checking and fault tolerance in arithmetic computations is facilitated when such redundant residues are used.

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“…The exact error location category can be identified and the error vector recovered simultaneously by checking the three computed syndrome values against six lookup tables in no more than three lookup cycles. The error detection tables can be implemented using pipelined multi-level lookup technique [Par97] to reduce the access time and simplify the address decoding circuit. The proposed algorithm has high parallelism and is the only algorithm that possesses a fixed and also the least number of iterations.…”

Section: Proof Of Uniquenessmentioning

confidence: 99%

New algorithms and VLSI architectures for efficient RNS computations

Tay¹

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Residue Number System (RNS) is a non-weighted number system emerging as a promising substitute of two's complement number system for data representation in high-speed and lowpower digital signal processing. In RNS, arithmetic operations, such as addition, subtraction and multiplication, can be carried out at a faster speed due to the avoidance of carry propagation. Nonetheless, the arithmetic operations such as sign detection, scaling, base transformation and error decoding, are generally more difficult to be implemented in RNS. This thesis aims to tackle these difficult RNS operations by designing simple and efficient algorithms and architectures. In this thesis, a fast and area efficient 2 n signed integer RNS scaler for the moduli set {2 n −1, 2 n , 2 n +1} is proposed. The complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. As a result, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup and 32.5% of total power reduction compared to the state-of-art designs. In addition, a new concept of base transformation is introduced to reduce the overall arithmetic processing costs of multi-base RNS. The exploration into this new concept is motivated by the overkill of arithmetic operator sizes in RNS-based digital signal processors (DSPs) due to the List of Abbreviations CRT Chinese Remainder Theorem CSA Carry Save Adder

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Modular reduction by multi-level table lookup

Cited by 10 publications

References 12 publications

Mathematical Model of the Process of Raising Integers to an Arbitrary Power of a Natural Number in the System of Residual Classes

Mathematical Model of the Process of Raising Integers to an Arbitrary Power of a Natural Number in the System of Residual Classes

Application of symmetric redundant residues for fast and reliable arithmetic

New algorithms and VLSI architectures for efficient RNS computations

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