Modular vector processor architecture targeting at data-level parallelism

Rooholamin, Seyed A.; Ziavras, Sotirios G.

doi:10.1016/j.micpro.2015.04.007

Cited by 5 publications

(1 citation statement)

References 22 publications

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“…This separation speeds up the most common memory access operations by avoiding extra delays and unnecessary stalls. In the lane-based VP design, each vector lane uses its own private memory to avoid any stalls during memory access instructions [11].…”

Section: Backgroundsmentioning

confidence: 99%

A Novel Vector-Scalar Architecture for Mobile Baseband Processing

Shen¹

2017

Proceedings of the 2nd Annual International Conference on Electronics, Electrical Engineering and Information Science (EEEIS 20

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The fast development of wireless communication protocols brings in big challenges for designing mobile baseband processor. In this paper, we propose a novel multi-core vector-scalar architecture with heuristic instruction set that can achieve high performance processing with budgeted power consumption and area cost across major computing blocks inside different communication protocols. This proposed architecture consists of four Vector-Scalar Engine Pairs (VSEPs). Each pair can support two data streams for multi-protocol application. The vector-scalar engine pair shares a common pipeline and the vector engine (VE) mainly deals with the symbol level data processing of wireless communication standard, such as OFDM (Orthogonal Frequency-Division Multiplexing) demodulation, while at the same time the scalar engine (SE) calculates the key parameters based on the heuristic instruction. We verify the performance of the architecture through benchmarking typical algorithms such as FFT (Fast Fourier Transform), Channel Estimation and MIMO (Multiple-Input Multiple-Output) detection. The results show that this proposed architecture can achieve better performance in average for 4G wireless communication.

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Section: Backgroundsmentioning

confidence: 99%

A Novel Vector-Scalar Architecture for Mobile Baseband Processing

Shen¹

2017

Proceedings of the 2nd Annual International Conference on Electronics, Electrical Engineering and Information Science (EEEIS 20

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VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.

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Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration

Rooholamin

Ziavras

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Modular vector processor architecture targeting at data-level parallelism

Cited by 5 publications

References 22 publications

A Novel Vector-Scalar Architecture for Mobile Baseband Processing

A Novel Vector-Scalar Architecture for Mobile Baseband Processing

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration

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