Modulation, control, and performance analysis of asymmetric modular multilevel converter (A‐MMC)

Abstract

Modular multilevel converters (MMC) have proven to be a viable candidate for high-voltage direct current transmission systems. Here, asymmetric modular multilevel converters (A-MMC) are introduced wherein each series connected module has two half-bridge (HB) submodules, with asymmetric voltage rating. Compared to conventional symmetric MMCs, such systems offer the following benefits: (i) generation of four distinct voltage levels using one module; (ii) 33% lesser semiconductor and gate drive requirement; (iii) higher system efficiency; (iv) reduction in overall cost and size. A hybrid pulsewidth modulation technique generates optimised switching pulses of the A-MMC. A novel voltage balancing algorithm is proposed to stabilise each asymmetric HB submodule at the rated voltage. Circulating current control is implemented to suppress the dominant second harmonic in the arm currents of the A-MMC. Detailed simulations in MATLAB/Simulink are performed to validate the operation and control. A quantitative and qualitative comparison with conventional MMCs is also presented in terms of the converter losses, output voltage/current total harmonic distortion, capacitor ripple voltages, circulating currents etc. Nomenclature M i ith module of A-MMC in a leg n number of modules in each arm ASM 1 submodule with capacitor at V C voltage ASM 2 submodule with capacitor at 2V C voltage S 1i state of any ith ASM 1 S 2i state of any ith ASM 2 v C1 capacitor voltage of ASM 1 (v¯C 1 = V C) v C2 capacitor voltage of ASM 2 (v¯C 2 = 2V C) v C1 max maximum capacitor voltage among all ASM 1 v C2 max maximum capacitor voltage among all ASM 2 v C1 ′ normalised voltage of ASM 1 = v C1 /V C v C2 ′ normalised voltage of ASM 2 = v C2 /2V C C 1 , C 2 capacitance of ASM 1 and ASM 2 L p , R p arm inductance and resistance L o , R o output inductance and resistance

Sensorless DTSMC of a three‐level VSI fed PMSM drive

“…These values should satisfy ((dσ α /dt) = (dσ β /dt) = 0). Accordingly, to prove proper speed estimation, the equivalent values are obtained by subtracting (30) and (31) from (26) and (27) di¯α s dt = 0 = ω e ψ βr − ω e ψ βr − μ α eq (39)…”

“…4, pp. 788-797 This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) multilevel topology, the cascaded H-bridge (CHB) inverter has modular structure and simple power circuit, resulting in higher reliability, thus preferred in variable frequency drives [25][26][27]. Hence, a three-level CHB VSI fed PMSM drive is used in this paper.…”

“…Recently, the multilevel inverters are preferred over conventional two‐level inverters due to several advantages like ability to synthesise near sinusoidal output voltage waveforms with low voltage rating switching devices, low dv/dt, improved total harmonic distortion (THD) and increased reliability. Among the multilevel topology, the cascaded H‐bridge (CHB) inverter has modular structure and simple power circuit, resulting in higher reliability, thus preferred in variable frequency drives [25–27]. Hence, a three‐level CHB VSI fed PMSM drive is used in this paper.…”

Control of Reduced Switches Count and Classical Multilevel Inverters: a Comparison

“…For a symmetric architecture, the amplitude of the continuous sources is identical. For an asymmetric architecture, the DC sources have different values [6], [7] to reach the maximum voltage. Moreover, producing a multilevel voltage with less THD requires several DC sources and several switches, which increases the complexity of the structure and the control.…”